ISL1209IU10Z-TK Datasheet ISL1209IU10Z-TK, ISL1209IU10Z, ISL1209IU10 | P16-P18

FN6109.4

October 17, 2006

DIGITAL TRIMMING REGISTER (DTR <2:0>)

The digital trimming bits DTR0, DTR1, and DTR2 adjust the

average number of counts per second and average the ppm

error to achieve better accuracy.

• DTR2 is a sign bit. DTR2 = “0” means frequency

compensation is >0. DTR2 = “1” means frequency

compensation is <0.

• DTR1 and DTR0 are both scale bits. DTR1 gives 40ppm

adjustment and DTR0 gives 20ppm adjustment.

A range from -60ppm to +60ppm can be represented by

using these three bits (see Table 13).

Note that the DTR adjustment will affect the frequency of the

clock at F

OUT

, for all frequency selections except for

32.768kHz. DTR can be used in conjunction with ATR and

OUT

to accurately set the oscillator frequency (see the

Applications Section).

Alarm Registers

Addresses [0Ch to 11h]

The alarm register bytes are set up identical to the RTC

an enable bit (enable = “1”). These enable bits specify which

alarm registers (seconds, minutes, etc.) are used to make

the comparison. Note that there is no alarm byte for year.

The alarm function works as a comparison between the

alarm registers and the RTC registers. As the RTC

advances, the alarm will be triggered once a match occurs

between the alarm registers and the RTC registers. Any one

alarm register, multiple registers, or all registers can be

enabled for a match.

There are two alarm operation modes: Single Event and

periodic Interrupt Mode:

• Single Event Mode is enabled by setting the ALME bit to

“1”, the IM bit to “0”, and disabling the frequency output.

This mode permits a one-time match between the alarm

registers and the RTC registers. Once this match occurs,

the ALM bit is set to “1” and the IRQ

output will be pulled

low and will remain low until the ALM bit is reset. This can

be done manually or by using the auto-reset feature.

• Interrupt Mode is enabled by setting the ALME bit to “1”,

the IM bit to “1”, and disabling the frequency output. The

IRQ

output will now be pulsed each time an alarm occurs.

This means that once the interrupt mode alarm is set, it will

continue to alarm for each occurring match of the alarm and

present time. This mode is convenient for hourly or daily

hardware interrupts in microcontroller applications such as

security cameras or utility meter reading.

To clear an alarm, the ALM bit in the status register must be

set to “0” with a write. Note that if the ARST bit is set to 1

(address 07h, bit 7), the ALM bit will automatically be cleared

when the status register is read.

Below are examples of both Single Event and periodic

Interrupt Mode alarms.

Example 1 – Alarm set with single interrupt (IM=”0”)

A single alarm will occur on January 1 at 11:30am.

A. Set Alarm registers as follows:

B. Also the ALME bit must be set as follows:

xx indicate other control bits

TABLE 12.

BMATR1 BMATR0

DELTA

CAPACITANCE

BAT

TO C

VDD

)

0 0 0pF

0 1 -0.5pF (≈ +2ppm)

1 0 +0.5pF (≈ -2ppm)

1 1 +1pF (≈ -4ppm)

TABLE 13. DIGITAL TRIMMING REGISTERS

DTR REGISTER ESTIMATED

FREQUENCY

PPMDTR2 DTR1 DTR0

0 0 0 0 (default)

001 +20

010 +40

011 +60

100 0

101 -20

110 -40

111 -60

ALARM

BIT

DESCRIPTION76543210HEX

SCA 00000000 00hSeconds disabled

MNA 10110000 B0hMinutes set to 30,

enabled

HRA 10010001 91hHours set to 11,

enabled

DTA 10000001 81hDate set to 1,

enabled

MOA 10000001 81hMonth set to 1,

enabled

DWA 00000000 00hDay of week

disabled

CONTROL

BIT

DESCRIPTION76543210HEX

INT 01xx0000 x0hEnable Alarm

ISL1209

FN6109.4

October 17, 2006

After these registers are set, an alarm will be generated when

the RTC advances to exactly 11:30am on January 1 (after

seconds changes from 59 to 00) by setting the ALM bit in the

status register to “1” and also bringing the IRQ

output low.

Example 2 – Pulsed interrupt once per minute (IM=”1”)

Interrupts at one minute intervals when the seconds register

is at 30 seconds.

A. Set Alarm registers as follows:

B. Set the Interrupt register as follows:

xx indicate other control bits

Once the registers are set, the following waveform will be

seen at IRQ-:

Note that the status register ALM bit will be set each time the

alarm is triggered, but does not need to be read or cleared.

User Registers

Addresses [12h to 13h]

These registers are 2 bytes of battery-backed user memory

storage.

C Serial Interface

The ISL1209 supports a bidirectional bus oriented protocol.

The protocol defines any device that sends data onto the

bus as a transmitter and the receiving device as the receiver.

The device controlling the transfer is the master and the

device being controlled is the slave. The master always

initiates data transfers and provides the clock for both

transmit and receive operations. Therefore, the ISL1209

operates as a slave device in all applications.

All communication over the I

C interface is conducted by

sending the MSB of each byte of data first.

Protocol Conventions

Data states on the SDA line can change only during SCL

LOW periods. SDA state changes during SCL HIGH are

reserved for indicating START and STOP conditions (See

Figure 12). On power up of the ISL1209, the SDA pin is in

the input mode.

All I

C interface operations must begin with a START

condition, which is a HIGH to LOW transition of SDA while

SCL is HIGH. The ISL1209 continuously monitors the SDA

and SCL lines for the START condition and does not

respond to any command until this condition is met (See

Figure 12). A START condition is ignored during the power-

up sequence.

All I

C interface operations must be terminated by a STOP

condition, which is a LOW to HIGH transition of SDA while

SCL is HIGH (See Figure 12). A STOP condition at the end

of a read operation or at the end of a write operation to

memory only places the device in its standby mode.

An acknowledge (ACK) is a software convention used to

indicate a successful data transfer. The transmitting device,

either master or slave, releases the SDA bus after

transmitting eight bits. During the ninth clock cycle, the

receiver pulls the SDA line LOW to acknowledge the

reception of the eight bits of data (See Figure 13).

The ISL1209 responds with an ACK after recognition of a

START condition followed by a valid Identification Byte, and

once again after successful receipt of an Address Byte. The

ISL1209 also responds with an ACK after receiving a Data

Byte of a write operation. The master must respond with an

ACK after receiving a Data Byte of a read operation.

ALARM

BIT

DESCRIPTION76543210HEX

SCA 10110000B0hSeconds set to 30,

enabled

MNA 0000000000hMinutes disabled

HRA 0000000000hHours disabled

DTA 0000000000hDate disabled

MOA 0000000000hMonth disabled

DWA 0000000000hDay of week disabled

CONTROL

BIT

DESCRIPTION76543210HEX

INT 11xx0000x0hEnable Alarm and Int

Mode

60 sec

RTC and alarm registers are both “30” sec

ISL1209

FN6109.4

October 17, 2006

FIGURE 12. VALID DATA CHANGES, START, AND STOP CONDITIONS

FIGURE 13. ACKNOWLEDGE RESPONSE FROM RECEIVER

FIGURE 14. BYTE WRITE SEQUENCE

SDA

SCL

START

DATA DATA

STOP

STABLE CHANGE

DATA

STABLE

SDA OUTPUT FROM

TRANSMITTER

SDA OUTPUT FROM

RECEIVER

81 9

START ACK

SCL FROM

MASTER

HIGH IMPEDANCE

IDENTIFICATION

BYTE

DATA

BYTE

SIGNALS FROM

THE MASTER

SIGNALS FROM

THE ISL1209

10011

WRITE

SIGNAL AT SDA

0000111

ADDRESS

BYTE

ISL1209

P1-P3 P4-P6 P7-P9 P10-P12 P13-P15 P16-P18 P19-P21 P22-P24

ISL1209IU10Z-TK

Mfr. #:

Buy ISL1209IU10Z-TK

Manufacturer:

Renesas / Intersil

Description:

Real Time Clock I2CAL TIME CLK/CLNDR W/EVENT DETCT 10LD

Lifecycle:

New from this manufacturer.

Delivery:

DHL FedEx Ups TNT EMS

Payment:

T/T Paypal Visa MoneyGram Western Union

ISL1209IU10Z-TK

ISL1209IU10Z-TK

Products related to this Datasheet