IDT5V49EE904
EEPROM PROGRAMMABLE CLOCK GENERATOR CLOCK SYNTHESIZER
IDT®
EEPROM PROGRAMMABLE CLOCK GENERATOR 4
IDT5V49EE904 REV Q 071015
1. When only an individual single-ended clock output is required, tie OUT# and OUT#b together.
2. Analog power plane should be isolated from a 3.3V power plane through a ferrite bead.
3. Each power pin should have a dedicated 0.01µF de-coupling capacitor. Digital VDDs may be tied together.
4. Unused clock inputs (REFIN or CLKIN) must be pulled high or low - they cannot be left floating. If the crystal oscillator is not used, XOUT must be left floating.
OUT1 7 O Adjustable Configurable clock output 1.Output levels controlled by
VDDO1.
OUT2 8 O Adjustable Configurable clock output 2. Output levels controlled by
VDDO1.
OUT3 24 O Adjustable Configurable clock output 3. Output levels controlled by
VDDO3.
OUT4 10 O Adjustable
1
Configurable clock output 4. Output levels controlled by
VDDO4.
OUT4b 11 O Adjustable
1
Configurable clock output 4b.Output levels controlled by
VDDO4.
OUT5 14 O Adjustable
1
Configurable clock output 5. Output levels controlled by
VDDO5.
OUT5b 15 O Adjustable
1
Configurable clock output 5b. Output levels controlled by
VDDO5.
OUT6 23 O Adjustable Configurable clock output 6. Output levels controlled by
VDDO3.
VDD
32 Power Device power supply. Connect to 3.3V.
VDDx
4 Power Crystal oscillator power supply. Connect to 3.3V through
5 resistor. Use filtered analog power supply if available.
AVDD
21 Power Device analog power supply. Connect to 3.3V. Use
filtered analog power supply if available.
VDDO1
9 Power Device power supply. Connect to 1.8 to 3.3V. Sets output
voltage levels for OUT1 and OUT2.
VDDO3
25 Power Device power supply. Connect to 1.8 to 3.3V. Sets output
voltage levels for OUT3 and OUT6.
VDDO4
12 Power Device power supply. Connect to 1.8 to 3.3V. Sets output
voltage levels for OUT4 and OUT4b.
VDDO5
16 Power Device power supply. Connect to 1.8 to 3.3V. Sets output
voltage levels for OUT5 and OUT5b.
GND 6, 13,
17, 22,
31,PAD
Power Connect to Ground.
Pin Name NL32
Pin#
I/O Pin Type Pin Description
IDT5V49EE904
EEPROM PROGRAMMABLE CLOCK GENERATOR CLOCK SYNTHESIZER
IDT®
EEPROM PROGRAMMABLE CLOCK GENERATOR 5
IDT5V49EE904 REV Q 071015
PLL Features and Descriptions
PLL0 Block Diagram
PLL1, PLL2 and PLL3 Block Diagram
VCO
N
D
A
Sigma-Delta
Modulator
12-bit
7-bit
4-bit
VCO
N
D
12-bit
7-bit
Pre-Divider
(D)
1
Values
Multiplier
(M)
2
Values
Programmable
Loop Bandwidth
Spread Spectrum
Generation Capability
PLL0 1 - 127 10 - 8206 Yes Yes
PLL1 1 - 127 1 - 4095 Yes No
PLL2 1 - 127 1 - 4095 Yes No
PLL3 3 - 127 12 - 4095 Yes Yes
1.For PLL0, PLL1 and PLL2, D=0 means PLL power down. For PLL3, 0, 1, and 2 are DNU (do not use)
2.For PLL0, M = 2*N + A + 1 (for A > 0); M = 2*N (for A = 0); A <
N-1. For PLL1, PLL2 and PLL3, M=N.
IDT5V49EE904
EEPROM PROGRAMMABLE CLOCK GENERATOR CLOCK SYNTHESIZER
IDT®
EEPROM PROGRAMMABLE CLOCK GENERATOR 6
IDT5V49EE904 REV Q 071015
Reference Clock Input Pins and
Selection
The IDT5V49EE904 supports up to two clock inputs. One of
the clock inputs (XIN/ REF) can be driven by either an
external crystal or a reference clock. The second clock input
(CLKIN) can only be driven from an external reference
clock. The CLKSEL pin selects the input clock from either
XTAL/REF or CLKIN.
Either clock input can be set as the primary clock. The
primary clock designation is to establish which is the main
reference clock to the PLLs. The non-primary clock is
designated as the secondary clock in case the primary clock
goes absent and a backup is needed. The PRIMSRC bit
(0xBE through 0xC3) determines which clock input will be
selected as primary clock. When PRIMSRC bit is "0",
XIN/REF is selected as the primary clock, and when "1",
CLKIN as the primary clock.
The two external reference clocks can be manually selected
using the CLKSEL pin. The SM bits (0xBE through 0xC3)
must be set to "0x" for manual switchover which is detailed
in SWITCHOVER MODES section.
Crystal Input (XIN/REF)
The crystal used should be a fundamental mode quartz
crystal; overtone crystals should not be used.
When the XIN/REF pin is driven by a crystal, it is important
to set the internal inverter oscillator drive strength and
tuning/load capacitor values correctly to achieve the best
clock performance. These values are programmable
through I
2
C interface to allow for maximum compatibility
with crystals from various manufacturers, processes,
performances, and qualities. The internal load capacitors
are true parallel-plate capacitors for ultra-linear
performance. Parallel-plate capacitors were chosen to
reduce the frequency shift that occurs when non-linear load
capacitance interacts with load, bias, supply, and
temperature changes. External non-linear crystal load
capacitors should not be used for applications that are
sensitive to absolute frequency requirements. The value of
the internal load capacitors are determined by XTAL[4:0]
bits. The load capacitance can be set with a resolution of
0.125 pF for a total crystal load ranging from 3.5 pF to 7.5
pF. Check with the crystal vendor's load capacitance
specification for the exact setting to tune the internal load
capacitor. The following equation governs how the total
internal load capacitance is set.
XTAL load cap = 3.5 pF + XTAL[4:0] * 0.125 pF (Eq. 1)
When using an external reference clock instead of a crystal
on the XTAL/REF pin, the input load capacitors may be
completely bypassed. This allows for the input frequency to
be up to 200 MHz. When using an external reference clock,
the XOUT pin must be left floating, XTAL must be
programmed to the default value of “00h”, and the crystal
drive strength bit, XDRV (0x06), must be set to the default
value of “11h”.
Switchover Modes
The IDT5V49EE904 features redundant clock inputs which
supports both Automatic and Manual switchover mode.
These two modes are determined by the configuration bits,
SM (0xBE through 0xC3). The primary clock source can be
programmed, via the PRIMSRC bit, to be either XIN/REF or
CLKIN. The other clock input will be considered as the
secondary source. Note that the switchover modes are
asynchronous. If the reference clocks are directly routed to
OUTx with no phase relationship, short pulses can be
generated during switchover. The automatic switchover
mode will work only when the primary clock source is
XIN/REF. Switchover modes are not supported for crystal
input configurations.
Manual Switchover Mode
When SM[1:0] is "0x", the redundant inputs are in manual
switchover mode. In this mode, CLKSEL pin is used to
switch between the primary and secondary clock sources.
As previously mentioned, the primary and secondary clock
source setting is determined by the PRIMSRC bit. During
the switchover, no glitches will occur at the output of the
device, although there may be frequency and phase drift,
depending on the exact phase and frequency relationship
between the primary and secondary clocks.
Automatic Switchover Mode
The redundant inputs are in automatic switchover mode.
Automatic switchover mode has revertive functionality. The
input clock selection will switch to the secondary clock
source when there are no transitions on the primary clock
source for two secondary clock cycles. If both reference
Parameter Bits Step (pF) Min (pF) Max (pF)
XTAL 8 0.125 0 4

5V49EE904NLGI

Mfr. #:
Manufacturer:
IDT
Description:
Clock Generators & Support Products EEPROM PROGRAMMABLE PLL
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New from this manufacturer.
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