Figure 8 - CML Input AC Coupled
Figure 9 - HCSL Input AC Coupled
ZL40204 Data Sheet
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Microsemi Corporation
VDD_driver
VDD_driver
VDD
ZL40204
clk_p
clk_n
CMOS
Driver
R
R
C
Vref = VDD_driver/2
For VDD_Driver = 2.5 or 3.3 V only
R=10 k ohm
Figure 10 - CMOS Input DC Coupled Referenced to VDD/2
VDD
VDD_driver
VDD
ZL40204
clk_p
clk_n
CMOS
Driver
R2
C
RA
R3
R1
Figure 11 - CMOS Input DC Coupled Referenced to Ground
Table 1 - Component Values for Single Ended Input Reference to Ground
VDD_driver R1 (k) R2 (k) R3 (k) RA (k) C (pF)
1.5 1.25 3.075 open 10 10
1.8 1 3.8 open 10 10
2.5 0.33 4.2 open 10 10
3.3 0.75 open 4.2 10 10
ZL40204 Data Sheet
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Microsemi Corporation
* For frequencies below 100 MHz, increase C to avoid signal integrity issues.
ZL40204 Data Sheet
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Microsemi Corporation
3.2 Clock Outputs
LVPECL has a very low output impedance and a differential signal swing between 1V and 1.6 V. A simplified
diagram for the output stage is shown in Figure 12.The LVPECL to LVDS output termination is not shown since
there is a separate device that has the same input and LVDS outputs.
Figure 12 - Simplified Output Driver
out_p
out_n
The methods to terminate the ZL40204 LVPECL drivers are shown in the following figures.
LVPECL
Receiver
50
Ohms
50
Ohms
VDD
VDD_Rx
Z
o
= 50 Ohms
Z
o
= 50 Ohms
ZL40204
clk_p
clk_n
VDD - 2
Figure 13 - LVPECL Basic Output Termination

ZL40204LDF1

Mfr. #:
Manufacturer:
Microchip / Microsemi
Description:
Clock Buffer 1:6 LVPECL Fanout Buffer w/Ext. Term.
Lifecycle:
New from this manufacturer.
Delivery:
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