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851021AYLF

P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18
REVISION C 11/03/15 13 1-TO-21, DIFFERENTIAL HCSL FANOUT BUFFER
851021 DATA SHEET
The purpose of this section is to calculate power dissipation on the IC per HCSL output pair.
HCSL output driver circuit and termination are shown in Figure 6.
VDD
V
OUT
R
L
50Ω
IC
➤
I
OUT
= 17mA
R
REF
=
950
Ω ± 1%
Figure 6. HCSL Driver Circuit and Termination
HCSL is a current steering output which sources a maximum of 17mA of current per output. To calculate worst case on-chip power dissipation,
use the following equations which assume a 50 load to ground.
The highest power dissipation occurs when V
DD
_
MAX
.
Power = (V
DD_MAX
– V
OUT
) * I
OUT
,
since V
OUT
= I
OUT
* R
L
= (V
DD_MAX
– I
OUT
* R
L
) * I
OUT
= (3.465V – 17mA * 50) * 17mA
Total Power Dissipation per output pair = 44
.5mW
1-TO-21, DIFFERENTIAL HCSL FANOUT BUFFER 14 REVISION C 11/03/15
851021 DATA SHEET
Reliability Information
Table 5.
JA
vs. Air Flow Table for a 64 Lead TQFP, E-Pad
Transistor Count
The transistor count for 851021 is: 843
JA
vs. Air Flow
Meters per Second 012.5
Multi-Layer PCB, JEDEC Standard Test Boards 31.8°C/W 25.8°C/W 24.2°C/W
REVISION C 11/03/15 15 1-TO-21, DIFFERENTIAL HCSL FANOUT BUFFER
851021 DATA SHEET
Package Outline and Package Dimensions
Package Outline - Y Suffix for 64 Lead TQFP, E-Pad
Table 6. Package Dimensions for 64 Lead TQFP, E-Pad
Reference Document: JEDEC Publication 95, MS-026
JEDEC Variation: ACD
All Dimensions in Millimeters
Symbol Minimum Nominal Maximum
N 64
A 1.20
A1 0.05 0.10 0.15
A2 0.95 1.00 1.05
b 0.17 0.22 0.27
c 0.09 0.20
D & E 12.00 Basic
D1 & E1 10.00 Basic
D2 & E2 7.50 Ref.
D3 & E3 4.5 5.5
e 0.50 Basic
L 0.45 0.60 0.75
0° 7°
ccc 0.08
-HD VERSION
EXPOSED PAD DOWN
P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18

851021AYLF

Mfr. #:
Buy 851021AYLF
Manufacturer:
IDT
Description:
Clock Drivers & Distribution 10 HCSL OUT BUFFER
Lifecycle:
New from this manufacturer.
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