1-TO-21, DIFFERENTIAL HCSL FANOUT BUFFER 4 REVISION C 11/03/15
851021 DATA SHEET
AC Electrical Characteristics
Table 3. HCSL AC Characteristics, V
DD
= 3.3V±5%, T
A
= 0°C to 70°C
NOTE: Electrical parameters are guaranteed over the specified ambient operating temperature range, which is established when the device is
mounted in a test socket with maintained transverse airflow greater than 500 lfpm. The device will meet specifications after thermal equilibrium
has been reached under these conditions.
NOTE: Current adjust set for V
OH
= 0.7V. Measurements refer to PCIEX outputs only.
NOTE: Characterized using an R
REF
value of 950 resistor.
NOTE 1: Measured from the differential input cross point to the differential output crossing point.
NOTE 2: Defined as skew between outputs at the same supply voltage and with equal load conditions. Measured at the differential output
cross point.
NOTE 3: This parameter is defined in accordance with JEDEC Standard 65.
NOTE 4: Defined as skew between outputs on different devices operating at the same supply voltage, same frequency, same temperature and
with equal load conditions. Using the same type of inputs on each device, the outputs are measured at the differential cross point.
NOTE 5: Output Drift is measured as the change in the time placement of the differential cross point for each output on a given device due to
a change in temperature and supply voltage. Measured at the differential cross point.
NOTE 6: Measurement using R
REF
= 950, R
LOAD
= 50..
NOTE 7: Measurement taken from single-ended waveform.
NOTE 8: Measured at crossing point where the instantaneous voltage value of the rising edge of Qx equals the falling edge of nQx.
See Parameter Measurement Information Section.
NOTE 9: Refers to the total variation from the lowest crossing point to the highest, regardless of which edge is crossing. Refers to all crossing
points for this measurement. See Parameter Measurement Information Section.
NOTE 10: Defined as the total variation of all crossing voltage of rising Qx and falling nQx. This is the maximum allowed variance in the
V
CROSS
for any particular system. See Parameter Measurement Information Section.
NOTE 11: Measurement taken from differential waveform.
NOTE 12: Measurement from -150mV to +150mV on the differential waveform (derived from Qx minus nQx). The signal must be monotonic
through the measurement region for rise and fall time. The 300mV measurement window is centered on the differential zero crossing.
NOTE 13: Matching applies to rising edge rate for Qx and falling edge rate for nQx. It is measured using a ±75mV window centered on the
median cross point where Qx rising meets nQx falling.
NOTE 14: Assuming 50% input duty cycle. Data taken at ƒ 200MHz, unless otherwise specified.
Symbol Parameter Test Conditions Minimum Typical Maximum Units
f
MAX
Output Frequency 250 MHz
t
PD
Propagation Delay, NOTE 1 Measured on at V
OX
1.5 2.75 ns
tsk(o) Output Skew; NOTE 2, 3 Measured on at V
OX
395 ps
tsk(pp) Part-to-Part Skew; NOTE 3, 4 335 ps
tjit
Buffer Additive Phase Jitter, RMS; refer
to Additive Phase Jitter Section
CLK = 200MHz, Integration
Range: 12kHz – 30MHz
0.20 ps
tsk(drift) Output Drift; NOTE 5 140 ps
V
MAX
Absolute Max Output Voltage; NOTE 6 ƒ 150MHz 500 850 mV
V
MIN
Absolute Min Output Voltage; NOTE 6 ƒ 150MHz -150 150 mV
V
CROSS
Absolute Crossing Voltage;
NOTE 7, 8, 9
250 550 mV
V
CROSS
Total Variation of V
CROSS
over all
edges; NOTE 7, 8, 10
140 mV
Rise/Fall Edge Rate; NOTE 11, 12 0.6 4.0 V/ns
Rise/Fall Time Matching; NOTE 13 20 %
odc Output Duty Cycle; NOTE 14 47 53 %
REVISION C 11/03/15 5 1-TO-21, DIFFERENTIAL HCSL FANOUT BUFFER
851021 DATA SHEET
Additive Phase Jitter
The spectral purity in a band at a specific offset from the fundamental
compared to the power of the fundamental is called the dBc Phase
Noise. This value is normally expressed using a Phase noise plot
and is most often the specified plot in many applications. Phase noise
is defined as the ratio of the noise power present in a 1Hz band at a
specified offset from the fundamental frequency to the power value of
the fundamental. This ratio is expressed in decibels (dBm) or a ratio
of the power in the 1Hz band to the power in the fundamental. When
the required offset is specified, the phase noise is called a dBc value,
which simply means dBm at a specified offset from the fundamental.
By investigating jitter in the frequency domain, we get a better
understanding of its effects on the desired application over the entire
time record of the signal. It is mathematically possible to calculate an
expected bit error rate given a phase noise plot.
As with most timing specifications, phase noise measurements has
issues relating to the limitations of the equipment. Often the noise
floor of the equipment is higher than the noise floor of the device. This
is illustrated above. The device meets the noise floor of what is
shown, but can actually be lower. The phase noise is dependent on
the input source and measurement equipment.
Additive Phase Jitter @ 200MHz
12kHz to 30MHz = 0.20ps (typical)
SSB Phase Noise dBc/Hz
Offset from Carrier Frequency (Hz)
1-TO-21, DIFFERENTIAL HCSL FANOUT BUFFER 6 REVISION C 11/03/15
851021 DATA SHEET
Parameter Measurement Information
HCSL Output Load AC Test Circuit
Differential Input Levels
Part-to-Part Skew
HCSL Output Load AC Test Circuit
Output Skew
Propagation Delay
Measurement
Point
33
Ω
50
Ω
50
Ω
33
Ω
Measurement
Point
49.9
Ω
49.9
Ω
HCSL
GND
2pF
2pF
V
DD
V
DD
V
CMR
Cross Points
V
PP
V
DD
GND
nCLK
CLK
nQx
Qx
nQy
Qy
tsk(pp)
Part 1
Part 2
950
Ω
50
Ω
50
Ω
HCSL
GND
0V
SCOPE
IREF
This load condition is used for I
DD,
tsk(pp), tjit(Ø), t
PD
and tsk(o)
measurements.
3.3V±5%
V
DD
nQx
Qx
nQy
Qy
t
PD
nCLK
CLK
nQ[0:20]
Q[0:20]

851021AYLF

Mfr. #:
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IDT
Description:
Clock Drivers & Distribution 10 HCSL OUT BUFFER
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