RT8070
10
DS8070-08 February 2015www.richtek.com
©
Copyright 2015 Richtek Technology Corporation. All rights reserved. is a registered trademark of Richtek Technology Corporation.
Figure 3. Derating Curve of Maximum Power Dissipation
Layout Considerations
Follow the PCB layout guidelines for optimal performance
of the IC.
Connect the terminal of the input capacitor(s), C
IN
, as
close to the VIN pin as possible. This capacitor provides
the AC current into the internal power MOSFETs.
LX node experiences high frequency voltage swings so
should be kept within a small area.
Keep all sensitive small signal nodes away from the LX
node to prevent stray capacitive noise pick up.
Connect the FB pin directly to the feedback resistors.
The resistive voltage divider must be connected between
V
OUT
and GND.
Figure 4. PCB Layout Guide
COMP
SS
EN
VIN
PGOOD
FB
LX
RT
GND
2
3
4
5
6
7
8
9
Place the compensation
components as close to
the IC as possible
V
OUT
GND
R2
R1
V
IN
C
IN
C
OUT
V
OUT
L1
R
COMP
C
COMP
LX should be connected
to inductor by wide and
short trace, and keep
sensitive components
away from this trace
Place the feedback
resistors as close to
the IC as possible
Place the input and output capacitors
as close to the IC as possible
GND
R
OSC
GND
C
SS
maximum power dissipation can be calculated by the
following formula :
P
D(MAX)
= (T
J(MAX)
− T
A
) / θ
JA
where T
J(MAX)
is the maximum junction temperature, T
A
is
the ambient temperature, and θ
JA
is the junction to ambient
thermal resistance.
For recommended operating condition specifications, the
maximum junction temperature is 125°C. The junction to
ambient thermal resistance, θ
JA
, is layout dependent. For
SOP-8 (Exposed Pad) packages, the thermal resistance,
θ
JA
, is 75°C/W on a standard JEDEC 51-7 four-layer
thermal test board. For WDFN-8L 3x3 packages, the
thermal resistance, θ
JA
, is 70°C/W on a standard JEDEC
51-7 four-layer thermal test board. The maximum power
dissipation at T
A
= 25°C can be calculated by the following
formulas :
P
D(MAX)
= (125°C − 25°C) / (75°C/W) = 1.333W for
SOP-8 (Exposed Pad) package
P
D(MAX)
= (125°C − 25°C) / (70°C/W) = 1.429W for
WDFN-8L 3x3 package
The maximum power dissipation depends on the operating
ambient temperature for fixed T
J(MAX)
and thermal
resistance, θ
JA
. The derating curves in Figure 3 allow the
designer to see the effect of rising ambient temperature
on the maximum power dissipation.
0.0
0.1
0.2
0.3
0.4
0.5
0.6
0.7
0.8
0.9
1.0
1.1
1.2
1.3
1.4
1.5
0 25 50 75 100 125
Ambient Temperature (°C)
Maximum Power Dissipation (W) 1
Four Layer PCB
WDFN-8L 3x3
SOP-8 (Exposed Pad)
Place the compensation
components as close to
the IC as possible
V
OUT
GND
R2
R1
V
IN
C
IN
C
OUT
V
OUT
L1
R
COMP
C
COMP
LX should be connected
to inductor by wide and
short trace, and keep
sensitive components
away from this trace
Place the feedback
resistors as close to
the IC as possible
Place the input and output capacitors
as close to the IC as possible
GND
R
OSC
GND
C
SS
COMP
SS
VIN
PGOOD
FB
RT
LX
EN
7
6
5
1
2
3
4
8
GND
9
(a) For SOP-8 (Exposed Pad) package
(b) For WDFN-8L 3x3 package
