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PCA9544AD,112

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PCA9544A All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved.
Product data sheet Rev. 5 — 23 April 2014 7 of 31
NXP Semiconductors
PCA9544A
4-channel I
2
C-bus multiplexer with interrupt logic
6.3 Interrupt handling
The PCA9544A provides 4 interrupt inputs, one for each channel and one open-drain
interrupt output. When an interrupt is generated by any device, it is detected by the
PCA9544A and the interrupt output is driven LOW. The channel need not be active for
detection of the interrupt. A bit is also set in the control byte. Bits 7:4 of the control byte
correspond to channel 3 to channel 0 of the PCA9544A, respectively. Therefore, if an
interrupt is generated by any device connected to channel 2, the state of the interrupt
inputs is loaded into the control register when a read is accomplished. Likewise, an
interrupt on any device connected to channel 0 would cause bit 4 of the control register to
be set on the read. The master can then address the PCA9544A and read the contents of
the control byte to determine which channel contains the device generating the interrupt.
The master can then reconfigure the PCA9544A to select this channel, and locate the
device generating the interrupt and clear it. The interrupt clears when the device
originating the interrupt clears.
It should be noted that more than one device can be providing an interrupt on a channel,
so it is up to the master to ensure that all devices on a channel are interrogated for an
interrupt.
If the interrupt function is not required, the interrupt inputs may be used as
general-purpose inputs.
If unused, interrupt inputs must be connected to V
DD
through a pull-up resistor.
Remark: Several interrupts can be active at the same time. For example: INT3 = 0,
INT2 = 1, INT1 = 1, INT0 = 0, means that there is no interrupt on channel 0 and
channel 3, and there is an interrupt on channel 1 and on channel 2.
Table 4. Control register: Write — channel selection; Read — channel status
INT3 INT2 INT1 INT0 D3 B2 B1 B0 Command
X X X X X 0 X X no channel selected
X X X X X 1 0 0 channel 0 enabled
X X X X X 1 0 1 channel 1 enabled
X X X X X 1 1 0 channel 2 enabled
X X X X X 1 1 1 channel 3 enabled
0 0 0 0 0 0 0 0 no channel selected;
power-up default state
Table 5. Control register read — interrupt
INT3 INT2 INT1 INT0 D3 B2 B1 B0 Command
XXX
0
XXXX
no interrupt on channel 0
1 interrupt on channel 0
XX
0
XXXXX
no interrupt on channel 1
1 interrupt on channel 1
X
0
XXXXXX
no interrupt on channel 2
1 interrupt on channel 2
0
XXXXXXX
no interrupt on channel 3
1 interrupt on channel 3
PCA9544A All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved.
Product data sheet Rev. 5 — 23 April 2014 8 of 31
NXP Semiconductors
PCA9544A
4-channel I
2
C-bus multiplexer with interrupt logic
6.4 Power-on reset
When power is applied to V
DD
, an internal Power-On Reset (POR) holds the PCA9544A in
a reset condition until V
DD
has reached V
POR
. At this point, the reset condition is released
and the PCA9544A registers and I
2
C-bus state machine are initialized to their default
states (all zeroes), causing all the channels to be deselected. Thereafter, V
DD
must be
lowered below 0.2 V for at least 5 s in order to reset the device.
6.5 Voltage translation
The pass gate transistors of the PCA9544A are constructed such that the V
DD
voltage can
be used to limit the maximum voltage that is passed from one I
2
C-bus to another.
Figure 7 shows the voltage characteristics of the pass gate transistors (note that the graph
was generated using the data specified in Section 12 “
Dynamic characteristics” of this
data sheet). In order for the PCA9544A to act as a voltage translator, the V
o(sw)
voltage
should be equal to, or lower than the lowest bus voltage. For example, if the main bus was
running at 5 V, and the downstream buses were 3.3 V and 2.7 V, then V
o(sw)
should be
equal to or below 2.7 V to effectively clamp the downstream bus voltages. Looking at
Figure 7
, we see that V
o(sw)(max)
is at 2.7 V when the PCA9544A supply voltage is 3.5 V or
lower so the PCA9544A supply voltage could be set to 3.3 V. Pull-up resistors can then be
used to bring the bus voltages to their appropriate levels (see Figure 14
).
More Information can be found in Application Note AN262, PCA954X family of I
2
C/SMBus
multiplexers and switches.
(1) maximum
(2) typical
(3) minimum
Fig 7. Pass gate voltage versus supply voltage
V
DD
(V)
2.0 5.54.53.0 4.0
002aaa964
3.0
2.0
4.0
5.0
V
o(sw)
(V)
1.0
3.5 5.02.5
(1)
(2)
(3)
PCA9544A All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved.
Product data sheet Rev. 5 — 23 April 2014 9 of 31
NXP Semiconductors
PCA9544A
4-channel I
2
C-bus multiplexer with interrupt logic
7. Characteristics of the I
2
C-bus
The I
2
C-bus is for 2-way, 2-line communication between different ICs or modules. The two
lines are a serial data line (SDA) and a serial clock line (SCL). Both lines must be
connected to a positive supply via a pull-up resistor when connected to the output stages
of a device. Data transfer may be initiated only when the bus is not busy.
7.1 Bit transfer
One data bit is transferred during each clock pulse. The data on the SDA line must remain
stable during the HIGH period of the clock pulse as changes in the data line at this time
will be interpreted as control signals (see Figure 8
).
7.2 START and STOP conditions
Both data and clock lines remain HIGH when the bus is not busy. A HIGH-to-LOW
transition of the data line while the clock is HIGH is defined as the START condition (S). A
LOW-to-HIGH transition of the data line while the clock is HIGH is defined as the STOP
condition (P) (see Figure 9
).
7.3 System configuration
A device generating a message is a ‘transmitter’, a device receiving is the ‘receiver’. The
device that controls the message is the ‘master’ and the devices which are controlled by
the master are the ‘slaves’ (see Figure 10
).
Fig 8. Bit transfer
Fig 9. Definition of START and STOP conditions
mba608
SDA
SCL
P
STOP condition
S
START condition
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PCA9544AD,112

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Buy PCA9544AD,112
Manufacturer:
NXP Semiconductors
Description:
Multiplexer Switch ICs 4-CH I2C MUX
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