NCP1573
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16
Layout Considerations
1. The fast response time of V
2
technology increases
the IC’s sensitivity to noise on the V
FB
line.
Fortunately, a simple RC filter, formed by the
feedback network and a small capacitor (100 pF
works well, shown below as C6) placed between
V
FB
and GND, filters out most noise and provides a
system practically immune to jitter. This capacitor
should be located as close as possible to the IC.
2. The COMP capacitor (shown below as C13)
should be connected via its own path to the IC
ground. The COMP capacitor is sensitive to the
intermittent ground drops caused by switching
currents. A separate ground path will reduce the
potential for jitter.
3. The V
CC
bypass capacitor (0.1 μF or greater,
shown below as C4) should be located as close as
possible to the IC. This capacitors connection to
GND must be as short as possible. The 10 Ω
resistor (shown below as R3) should be placed
close to the V
CC
pin.
4. The IC should not be placed in the path of
switching currents. If a ground plane is used, care
should be taken by the designer to ensure that the
IC is not located over a ground or other current
return path.
Figure 26.
V
OUT
R4
R6
C6
C4
R3
GND
12 V PWRGD
R1
U1
5 V
C13
C12
NCP1573
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17
PACKAGE DIMENSIONS
SO8
D SUFFIX
CASE 75107
ISSUE W
SEATING
PLANE
1
4
58
N
J
X 45
_
K
NOTES:
1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.
2. CONTROLLING DIMENSION: MILLIMETER.
3. DIMENSION A AND B DO NOT INCLUDE MOLD
PROTRUSION.
4. MAXIMUM MOLD PROTRUSION 0.15 (0.006) PER
SIDE.
5. DIMENSION D DOES NOT INCLUDE DAMBAR
PROTRUSION. ALLOWABLE DAMBAR
PROTRUSION SHALL BE 0.127 (0.005) TOTAL IN
EXCESS OF THE D DIMENSION AT MAXIMUM
MATERIAL CONDITION.
A
B
S
D
H
C
0.10 (0.004)
X
Y
G
M
Y
M
0.25 (0.010)
Z
Y
M
0.25 (0.010) Z
S
X
S
M
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V
2
is a trademark of Switch Power, Inc.

NCP1573DR2

Mfr. #:
Manufacturer:
ON Semiconductor
Description:
IC REG CTRLR BUCK 8SOIC
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