PCA9547 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved.
Product data sheet Rev. 4 — 1 April 2014 4 of 30
NXP Semiconductors
PCA9547
8-channel I
2
C-bus multiplexer with reset
5. Pinning information
5.1 Pinning
Fig 2. Pin configuration for SO24 Fig 3. Pin configuration for TSSOP24
Fig 4. Pin configuration for HVQFN24 (transparent top view)
PCA9547D
A0 V
DD
A1 SDA
RESET SCL
SD0 A2
SC0 SC7
SD1 SD7
SC1 SC6
SD2 SD6
SC2 SC5
SD3 SD5
SC3 SC4
V
SS
SD4
002aaa958
1
2
3
4
5
6
7
8
9
10
11
12
14
13
16
15
18
17
20
19
22
21
24
23
PCA9547PW
A0 V
DD
A1 SDA
RESET SCL
SD0 A2
SC0 SC7
SD1 SD7
SC1 SC6
SD2 SD6
SC2 SC5
SD3 SD5
SC3 SC4
V
SS
SD4
002aaa959
1
2
3
4
5
6
7
8
9
10
11
12
14
13
16
15
18
17
20
19
22
21
24
23
002aaa960
PCA9547BS
Transparent top view
SC5
SD2
SC2
SD6
SC1 SC6
SD1 SD7
SC0 SC7
SD0 A2
SD3
SC3
V
SS
SD4
SC4
SD5
RESET
A1
A0
V
DD
SDA
SCL
terminal 1
index area
6
13
5
14
4 15
3 16
2 17
1
18
7
8
9
10
11
12
24
23
22
21
20
19
PCA9547 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved.
Product data sheet Rev. 4 — 1 April 2014 5 of 30
NXP Semiconductors
PCA9547
8-channel I
2
C-bus multiplexer with reset
5.2 Pin description
[1] HVQFN24 package die supply ground is connected to both the V
SS
pin and the exposed center pad. The
V
SS
pin must be connected to supply ground for proper device operation. For enhanced thermal, electrical,
and board-level performance, the exposed pad needs to be soldered to the board using a corresponding
thermal pad on the board, and for proper heat conduction through the board thermal vias need to be
incorporated in the PCB in the thermal pad region.
Table 3. Pin description
Symbol Pin Description
SO24, TSSOP24 HVQFN24
A0 1 22 address input 0
A1 2 23 address input 1
RESET
3 24 active LOW reset input
SD0 4 1 serial data output 0
SC0 5 2 serial clock output 0
SD1 6 3 serial data output 1
SC1 7 4 serial clock output 1
SD2 8 5 serial data output 2
SC2 9 6 serial clock output 2
SD3 10 7 serial data output 3
SC3 11 8 serial clock output 3
V
SS
12 9
[1]
supply ground
SD4 13 10 serial data output 4
SC4 14 11 serial clock output 4
SD5 15 12 serial data output 5
SC5 16 13 serial clock output 5
SD6 17 14 serial data output 6
SC6 18 15 serial clock output 6
SD7 19 16 serial data output 7
SC7 20 17 serial clock output 7
A2 21 18 address input 2
SCL 22 19 serial clock line
SDA 23 20 serial data line
V
DD
24 21 supply voltage
PCA9547 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved.
Product data sheet Rev. 4 — 1 April 2014 6 of 30
NXP Semiconductors
PCA9547
8-channel I
2
C-bus multiplexer with reset
6. Functional description
6.1 Device addressing
Following a START condition, the bus master must output the address of the slave it is
accessing. The address of the PCA9547 is shown in Figure 5
. To conserve power, no
internal pull-up resistors are incorporated on the hardware selectable address pins and
they must be pulled HIGH or LOW.
The last bit of the slave address defines the operation to be performed. When set to
logic 1 a read is selected, while a logic 0 selects a write operation.
6.2 Control register
Following the successful acknowledgement of the slave address, the bus master will send
a byte to the PCA9547, which will be stored in the Control register. If multiple bytes are
received by the PCA9547, it will save the last byte received. This register can be written
and read via the I
2
C-bus.
6.2.1 Control register definition
A SCx/SDx downstream pair, or channel, is selected by the contents of the control
register. This register is written after the PCA9547 has been addressed. The 4 LSBs of
the control byte are used to determine which channel is to be selected. When a channel is
selected, the channel will become active after a STOP condition has been placed on the
I
2
C-bus. This ensures that all SCx/SDx lines will be in a HIGH state when the channel is
made active, so that no false conditions are generated at the time of connection.
Fig 5. Slave address
002aaa962
1 1 1 0 A2 A1 A0 R/W
fixed hardware
selectable
Fig 6. Control register
002aaa963
X X X X B3 B2 B1 B0
channel selection bits
(read/write)
76543210
enable bit

PCA9547BS,118

Mfr. #:
Manufacturer:
NXP Semiconductors
Description:
Encoders, Decoders, Multiplexers & Demultiplexers 8-CH I2C MUX W/RESET
Lifecycle:
New from this manufacturer.
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