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PCA9547BS,118

P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21P22-P24P25-P27P28-P30
PCA9547 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved.
Product data sheet Rev. 4 — 1 April 2014 7 of 30
NXP Semiconductors
PCA9547
8-channel I
2
C-bus multiplexer with reset
6.3 RESET input
The RESET input is an active LOW signal which may be used to recover from a bus fault
condition. By asserting this signal LOW for a minimum of t
w(rst)L
, the PCA9547 will reset its
register and I
2
C-bus state machine and will deselect all channels except channel 0. The
RESET
input must be connected to V
DD
through a pull-up resistor.
6.4 Power-on reset
When power is applied to V
DD
, an internal Power-On Reset (POR) holds the PCA9547 in
a reset condition until V
DD
has reached V
POR
. At this point, the reset condition is released
and the PCA9547 register and I
2
C-bus state machine are initialized to their default states,
causing all the channels to be deselected except channel 0. Thereafter, V
DD
must be
lowered below 0.2 V for at least 5 s in order to reset the device.
Table 4. Control register
Write = channel selection; Read = channel status
D7 D6 D5 D4 B3 B2 B1 B0 Command
XXXX0XXXno channel selected
XXXX1000channel0 enabled
XXXX1001channel1 enabled
XXXX1010channel2 enabled
XXXX1011channel3 enabled
XXXX1100channel4 enabled
XXXX1101channel5 enabled
XXXX1110channel6 enabled
XXXX1111channel7 enabled
00001000channel 0 enabled;
power-up/reset default state
PCA9547 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved.
Product data sheet Rev. 4 — 1 April 2014 8 of 30
NXP Semiconductors
PCA9547
8-channel I
2
C-bus multiplexer with reset
6.5 Voltage translation
The pass gate transistors of the PCA9547 are constructed such that the V
DD
voltage can
be used to limit the maximum voltage that will be passed from one I
2
C-bus to another.
Figure 7 shows the voltage characteristics of the pass gate transistors (note that the
PCA9547 is only tested at the points specified in Section 11 “
Static characteristics” of this
data sheet). In order for the PCA9547 to act as a voltage translator, the V
o(mux)
voltage
should be equal to, or lower than the lowest bus voltage. For example, if the main bus was
running at 5 V, and the downstream buses were 3.3 V and 2.7 V, then V
o(mux)
should be
equal to or below 2.7 V to effectively clamp the downstream bus voltages. Looking at
Figure 7
, we see that V
o(mux)(max)
will be at 2.7 V when the PCA9547 supply voltage is
3.5 V or lower so the PCA9547 supply voltage could be set to 3.3 V. Pull-up resistors can
then be used to bring the bus voltages to their appropriate levels (see Figure 14
).
More information can be found in Application Note AN262, PCA954X family of I
2
C/SMBus
multiplexers and switches.
(1) maximum
(2) typical
(3) minimum
Fig 7. Pass gate voltage as a function of supply voltage
V
DD
(V)
2.0 5.54.53.0 4.0
002aab802
3.0
2.0
4.0
5.0
V
o(mux)
(V)
1.0
3.5 5.02.5
(1)
(2)
(3)
PCA9547 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved.
Product data sheet Rev. 4 — 1 April 2014 9 of 30
NXP Semiconductors
PCA9547
8-channel I
2
C-bus multiplexer with reset
7. Characteristics of the I
2
C-bus
The I
2
C-bus is for 2-way, 2-line communication between different ICs or modules. The two
lines are a serial data line (SDA) and a serial clock line (SCL). Both lines must be
connected to a positive supply via a pull-up resistor when connected to the output stages
of a device. Data transfer may be initiated only when the bus is not busy.
7.1 Bit transfer
One data bit is transferred during each clock pulse. The data on the SDA line must remain
stable during the HIGH period of the clock pulse as changes in the data line at this time
will be interpreted as control signals (see Figure 8
).
7.1.1 START and STOP conditions
Both data and clock lines remain HIGH when the bus is not busy. A HIGH-to-LOW
transition of the data line while the clock is HIGH is defined as the START condition (S). A
LOW-to-HIGH transition of the data line while the clock is HIGH is defined as the STOP
condition (P) (seeFigure 9
.)
Fig 8. Bit transfer
Fig 9. Definition of START and STOP conditions
mba608
SDA
SCL
P
STOP condition
S
START condition
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PCA9547BS,118

Mfr. #:
Buy PCA9547BS,118
Manufacturer:
NXP Semiconductors
Description:
Encoders, Decoders, Multiplexers & Demultiplexers 8-CH I2C MUX W/RESET
Lifecycle:
New from this manufacturer.
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