IS31FL3726
Integrated Silicon Solution, Inc. — www.issi.com
Rev.B, 06/18/2013
6
n = 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
CLOCK
SERIAL-IN
LATCH
ENABLE
OUT0
OUT1
OUT2
OUT15
SERIAL-OUT
H
L
H
L
H
L
H
L
ON
OFF
ON
OFF
ON
OFF
ON
OFF
H
L
Figure 3 Timing Dagram
Warning:
Latch circuit is leveled-latch circuit. Be careful because it is not triggered-latch circuit.
Note : The latches circuit holds data by pulling the L A T C H
————————
terminal Low. And, when L A T C H
————————
terminal is a High level, latch circuit
doesn’t hold data, and it passes from the input to the output. When E N A B L E
—————————
terminal is a Low level, output terminal O U T 0
——————
to O U T 1 5
———————
respond to the data, and on and off does. And, when E N A B L E
—————————
terminal is a High level, it offs with the output terminal regardless of the
data.
Truth Table
CLOCK
LATCH
————————
ENABLE
—————————
SERIAL-IN
OUT0
——————
…
OUT7
——————
…
OUT15
———————
SERIAL-OUT
H L Dn Dn …Dn-7 …Dn-15 Dn-15
L L Dn+1 No change Dn-14
H L Dn+2 Dn+2 …Dn-5 …Dn-13 Dn-13
X L Dn+3 Dn+2 …Dn-5 …Dn-13 Dn-13
X H Dn+3 OFF Dn-13
Note : OUT0
—————
to OUT15
—————
=On when Dn = H; OUT0
—————
to OUT15
—————
=Off when Dn = L. In order to ensure that the level of the power supply
voltage is correct, an external resistor must be connected between R-EXT and GND.
Warning: The following conditions, ENABLE
____________
=0, LATCH
__________
=1, SERIAL-IN=1, cannot be configured at the same time when power on, or
IS31FL3726 will be abnormal.