BUK9832-55A All information provided in this document is subject to legal disclaimers. © NXP B.V. 2010. All rights reserved.
Product data sheet Rev. 02 — 1 June 2010 3 of 13
NXP Semiconductors
BUK9832-55A
N-channel TrenchMOS logic level FET
4. Limiting values
Table 4. Limiting values
In accordance with the Absolute Maximum Rating System (IEC 60134).
Symbol Parameter Conditions Min Typ Max Unit
V
DS
drain-source voltage T
j
≥ 25 °C; T
j
≤ 150°C --55V
V
DGR
drain-gate voltage R
GS
=20kΩ --55V
V
GS
gate-source voltage -10 - 10 V
I
D
drain current T
sp
=25°C; V
GS
= 5 V; see Figure 1;
see Figure 3
--12A
T
sp
= 100 °C; V
GS
=5V; see Figure 1 --7A
I
DM
peak drain current T
sp
=25°C; t
p
≤ 10 µs; pulsed;
see Figure 3
--47A
P
tot
total power dissipation T
sp
=25°C; see Figure 2 --8W
T
stg
storage temperature -55 - 150 °C
T
j
junction temperature -55 - 150 °C
V
GSM
peak gate-source
voltage
pulsed; t
p
≤ 50 µs -15 - 15 V
Source-drain diode
I
S
source current T
sp
=25°C --12A
I
SM
peak source current t
p
≤ 10 µs; pulsed; T
sp
=25°C --47A
Avalanche ruggedness
E
DS(AL)S
non-repetitive
drain-source
avalanche energy
I
D
=10A; V
sup
≤ 55 V; R
GS
=50Ω;
V
GS
=5V; T
j(init)
= 25 °C; unclamped
- - 100 mJ
Fig 1. Normalized continuous drain current as a
function of solder point temperature
Fig 2. Normalized total power dissipation as a
function of solder point temperature
T
sp
(°C)
0 20015050 100
03aa25
40
80
120
I
der
(%)
0
T
sp
(°C)
0 20015050 100
03aa17
40
80
120
P
der
(%)
0
