OMO ElectronicOMO Electronic
Expand menu
Hello, Sign inMy Account
0 Cart

AD7405BRIZ-RL7

P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21
AD7405 Data Sheet
TERMINOLOGY
Differential Nonlinearity (DNL)
DNL is the difference between the measured and the ideal
1 LSB change between any two adjacent codes in the ADC.
Integral Nonlinearity (INL)
INL is the maximum deviation from a straight line passing
through the endpoints of the ADC transfer function. The
endpoints of the transfer function are a specified negative full
scale, −250 mV (V
IN+
− V
IN−
), Code 7168 for the 16-bit level,
and a specified positive full scale, +250 mV (V
IN+
− V
IN−
),
Code 58,368 for the 16-bit level.
Offset Error
Offset error is the deviation of the midscale code (32,768 for the
16-bit level) from the ideal V
IN+
− V
IN−
(that is, 0 V).
Gain Error
The gain error includes both positive full-scale gain error and
negative full-scale gain error. Positive full-scale gain error is the
deviation of the specified positive full-scale code (58,368 for the
16-bit level) from the ideal V
IN+
− V
IN−
(250 mV) after the offset
error is adjusted out. Negative full-scale gain error is the
deviation of the specified negative full-scale code (7168 for the
16-bit level) from the ideal V
IN+
− V
IN−
(−250 mV) after the
offset error is adjusted out.
Signal-to-Noise-and-Distortion Ratio (SINAD)
SINAD is the measured ratio of signal-to-noise-and-distortion
at the output of the ADC. The signal is the rms value of the sine
wave, and noise is the rms sum of all nonfundamental signals
up to half the sampling frequency (f
S
/2), including harmonics,
but excluding dc.
Signal-to-Noise Ratio (SNR)
SNR is the measured signal-to-noise ratio at the output of the
ADC. The signal is the rms amplitude of the fundamental. Noise
is the sum of all nonfundamental signals up to half the sampling
frequency (f
S
/2), excluding dc.
The ratio is dependent on the number of quantization levels in the
digitization process: the greater the number of levels, the smaller
the quantization noise. The theoretical SNR for an ideal N-bit
converter with a sine wave input is given by
Signal-to-Noise Ratio = (6.02N + 1.76) dB
Therefore, for a 12-bit converter, the SNR is 74 dB.
Isolation Transient Immunity
The isolation transient immunity specifies the rate of rise and
fall of a transient pulse applied across the isolation boundary,
beyond which clock or data is corrupted. The AD7405 was
tested using a transient pulse frequency of 100 kHz.
Total Harmonic Distortion (THD)
THD is the ratio of the rms sum of harmonics to the
fundamental. For the AD7405, it is defined as
1
6
54
32
V
VVVVV
THD
22222
log20(dB)
++++
=
w
here:
V
1
is the rms amplitude of the fundamental.
V
2
, V
3
, V
4
, V
5
, and V
6
are the rms amplitudes of the second
through the sixth harmonics.
Peak Harmonic or Spurious Noise
Peak harmonic or spurious noise is defined as the ratio of the
rms value of the next largest component in the ADC output
spectrum (up to f
S
/2, excluding dc) to the rms value of the
fundamental. Normally, the value of this specification is
determined by the largest harmonic in the spectrum, but for
ADCs where the harmonics are buried in the noise floor, it is a
noise peak.
Effective Number of Bits (ENOB)
ENOB is defined by
ENOB = (SINAD − 1.76)/6.02 bits
Noise Free Code Resolution
Noise free code resolution represents the resolution in bits for
which there is no code flicker. The noise free code resolution
for an N-bit converter is defined as
Noise Free Code Resolution (Bits) = log
2
(2
N
/Peak-to-Peak Noise)
The peak-to-peak noise in LSBs is measured with V
IN+
= V
IN−
= 0 V.
Common-Mode Rejection Ratio (CMRR)
CMRR is defined as the ratio of the power in the ADC output at
±250 mV frequency, f, to the power of a +250 mV peak-to-peak
sine wave applied to the common-mode voltage of V
IN+
and V
IN−
of frequency, f
S
, as
CMRR (dB) = 10 log(Pf/Pf
S
)
where:
Pf is the power at frequency, f, in the ADC output.
Pf
S
is the power at frequency, f
S
, in the ADC output.
Power Supply Rejection Ratio (PSRR)
Variations in power supply affect the full-scale transition but
not the linearity of the converter. PSRR is the maximum change
in the specified full-scale (±250 mV) transition point due to a
change in power supply voltage from the nominal value.
Rev. A | Page 12 of 20
Data Sheet AD7405
THEORY OF OPERATION
CIRCUIT INFORMATION
The AD7405 isolated Σ-Δ modulator converts an analog input
signal into a high speed (20 MHz maximum), single-bit data
stream; the time average single-bit data from the modulator is
directly proportional to the input signal. Figure 21 shows a
typical application circuit where the AD7405 is used to provide
isolation between the analog input, a current sensing resistor or
shunt, and the digital output, which is then processed by a
digital filter to provide an N-bit word.
ANALOG INPUT
The differential analog input of the AD7405 is implemented
with a switched capacitor circuit. This circuit implements a
second-order modulator stage that digitizes the input signal
into a single-bit output stream. The sample clock (MCLKIN)
provides the clock signal for the conversion process as well as
the output data framing clock. This clock source is external on
the AD7405. The analog input signal is continuously sampled
by the modulator and compared to an internal voltage
reference. A digital stream that accurately represents the
analog input over time appears at the output of the converter
(see Figure 22).
A differential input signal of 0 V ideally results in a differential
stream of alternating 1s and 0s at the MDAT± output pins. This
output is high 50% of the time and low 50% of the time. A
differential input of 250 mV produces a stream of 1s and 0s that
are high 89.06% of the time. A differential input of −250 mV
produces a stream of 1s and 0s that are high 10.94% of the time.
A differential input of 320 mV ideally results in a stream of all
1s. A differential input of −320 mV ideally results in a stream of
all 0s. The absolute full-scale range is ±320 mV, and the specified
full-scale performance range is ±250 mV, as shown in Table 10.
Table 10. Analog Input Range
Analog Input Voltage Input (mV)
Positive Full-Scale Value +320
Positive Specified Performance Input +250
Zero 0
Negative Specified Performance Input −250
Negative Full-Scale Value −320
F
igure 21. Typical Application Circuit
F
igure 22. Analog Input vs. Modulator Output
Σ-Δ
MOD/
ENCODER
NONISOLATED
5V/3V
V
DD1
GND
1
V
IN+
V
IN–
GND
1
V
DD1
V
DD
GND
V
DD2
MDAT+
MDAT–
MDAT
SINC3 FILTER*
AD7405
MCLKIN+
SDAT
CS
SCLK
MCLKIN–
MCLK
100nF
GND
2
DECODER
1nF10µF
+400V
–400V
220pF
220pF
10Ω
5.1V
R
SHUNT
10Ω
DECODER
ENCODER
1nF10µF
GATED
DRIVE
CIRCUIT
FLOATING
POWER SUPPLY
GATED
DRIVE
CIRCUIT
FLOATING
POWER SUPPLY
MOTOR
*THIS FILTER IS IMPLEMENTED
WITH AN FPGA OR DSP
100Ω
100Ω
12536-021
MODULATOR OUTPUT
+FS ANALOG INPUT
–FS ANALOG INPUT
ANALOG INPUT
12536-022
Rev. A | Page 13 of 20
AD7405 Data Sheet
To reconstruct the original information, this output must be
digitally filtered and decimated. A sinc3 filter is recommended
because it is one order higher than that of the AD7405 modulator,
which is a second-order modulator. If a 256 decimation rate is
used, the resulting 16-bit word rate is 78.1 kSPS, assuming a
20 MHz external clock frequency. See the Digital Filter section
for more detailed information on the sinc filter implementation.
Figure 23 shows the transfer function of the AD7405 relative to
the 16-bit output.
F
igure 23. Filtered and Decimated 16-Bit Transfer Function
DIFFERENTIAL INPUTS
The analog input to the modulator is a switched capacitor
design. The analog signal is converted into charge by highly
linear sampling capacitors. A simplified equivalent circuit
diagram of the analog input is shown in Figure 24. A signal
source driving the analog input must provide the charge onto
the sampling capacitors every half MCLKIN cycle and settle to the
required accuracy within the next half cycle.
F
igure 24. Analog Input Equivalent Circuit
Because the AD7405 samples the differential voltage across its
analog inputs, an input circuit provides low common-mode
noise at each input attaining low noise performance.
LOW VOLTAGE DIFFERENTIAL SIGNALING (LVDS)
INTERFACE
The AD7405 uses an LVDS interface for both the clock input
and the modulator output. The benefits of using LVDS in this
case helps to make the interface between the modulator and the
controller more robust and less susceptible to electromagnetic
interference (EMI) from the surroundings. LVDS also helps to
reduce the EMI emissions associated with high speed digital
signaling. LVDS signals are treated like transmission lines and
must be resistively terminated. The value of the differential
terminating resistor is typically 100 Ω. Place the terminating
resistor as close to the receiver as possible.
65535
58368
SPECIFIED RANGE
ANALOG INPUT
ADC CODE
7168
–320mV –250mV +250mV +320mV
0
12536-023
φA
φB
300Ω
V
IN–
φA
φB
φB φB
300Ω
V
IN+
1.9pF
1.9pF
φA φA
MCLKIN
12536-024
Rev. A | Page 14 of 20
P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21

AD7405BRIZ-RL7

Mfr. #:
Buy AD7405BRIZ-RL7
Manufacturer:
Analog Devices Inc.
Description:
Analog to Digital Converters - ADC Iso-16Bit SigmaDelta ADC Ext Clk LVDS
Lifecycle:
New from this manufacturer.
Delivery:
DHL FedEx Ups TNT EMS
Payment:
T/T Paypal Visa MoneyGram Western Union

Products related to this Datasheet