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AD7405BRIZ-RL7

P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21
Data Sheet AD7405
APPLICATIONS INFORMATION
CURRENT SENSING APPLICATIONS
The AD7405 is ideally suited for current sensing applications
where the voltage across a shunt resistor (R
SHUNT
) is monitored.
The load current flowing through an external shunt resistor
produces a voltage at the input terminals of the AD7405. The
AD7405 provides isolation between the analog input from the
current sensing resistor and the digital outputs. By selecting the
appropriate shunt resistor value, a variety of current ranges can
be monitored.
Choosing R
SHUNT
The shunt resistor (R
SHUNT
) values used in conjunction with the
AD7405 are determined by the specific application requirements
in terms of voltage, current, and power. Small resistors minimize
power dissipation, whereas low inductance resistors prevent any
induced voltage spikes, and good tolerance devices reduce
current variations. The final values chosen are a compromise
between low power dissipation and accuracy. Higher value
resistors use the full performance input range of the ADC, thus
achieving maximum SNR performance. Low value resistors
dissipate less power but do not use the full performance input
range. The AD7405, however, delivers excellent performance,
even with lower input signal levels, allowing low value shunt
resistors to be used while maintaining system performance.
To choose a suitable shunt resistor, first determine the current
through the shunt. The shunt current for a 3-phase induction
motor can be expressed as
PFEFV
P
I
W
RMS
×××
=
73.1
w
here:
I
RMS
is the motor phase current (A rms).
P
W
is the motor power (Watts).
V is the motor supply voltage (V ac).
EF is the motor efficiency (%).
PF is the power efficiency (%).
To determine the shunt peak sense current, I
SENSE
, consider the
motor phase current and any overload that may be possible in
the system. When the peak sense current is known, divide the
voltage range of the AD7405 (±250 mV) by the peak sense
current to yield a maximum shunt value.
If the power dissipation in the shunt resistor is too large, the
shunt resistor can be reduced and less of the ADC input range can
be used. Figure 25 shows the SINAD performance characteristics
and the ENOB of resolution for the AD7405 for different input
signal amplitudes. Figure 26 shows the rms noise performance
for dc input signal amplitudes. The AD7405 performance at
lower input signal ranges allows smaller shunt values to be used
while still maintaining a high level of performance and overall
system efficiency.
F
igure 25. SINAD vs. V
IN+
AC Input Signal Amplitude
F
igure 26. RMS Noise vs. V
IN+
DC Input Signal Amplitude
R
SHUNT
must be able to dissipate the I2R power losses. If the
power dissipation rating of the resistor is exceeded, its value
may drift or the resistor may be damaged, resulting in an open
circuit. This open circuit can result in a differential voltage
across the terminals of the AD7405, in excess of the absolute
maximum ratings. If I
SENSE
has a large, high frequency
component, choose a resistor with low inductance.
VOLTAGE SENSING APPLICATIONS
The AD7405 can also be used for isolated voltage monitoring.
For example, in motor control applications, it can be used to
sense the bus voltage. In applications where the voltage being
monitored exceeds the specified analog input range of the
AD7405, a voltage divider network can be used to reduce the
voltage being monitored to the required range.
60
65
70
75
80
85
90
0 50 100 150 200 250
SINAD (dB)
V
IN+
AC INPUT SIGNAL AMPLITUDE (mV)
14 -BIT
ENOB
11-BIT
ENOB
12-BIT
ENOB
13-BIT
ENOB
f
IN
= 1kHz
T
A
= 25°C
MCLKIN = 20MHz
V
DD1
= 5V
V
DD2
= 5V
12536-025
0
0.2
0.4
0.6
0.8
1.0
1.2
1.4
1.6
–320 –240 –160 –80 0 80 160 240 320
RMS NOISE (LSB)
MCLKIN = 5MHz
MCLKIN = 10MHz
MCLKIN = 20MHz
V
IN+
DC INPUT SIGNAL AMPLITUDE (mV)
DC INPUT
100k SAMPLES PER DATA POINT
12536-026
Rev. A | Page 15 of 20
AD7405 Data Sheet
INPUT FILTER
In a typical application, where voltage is being measured across
a shunt resistor, connect the AD7405 directly across the shunt
resistor with a simple RC low-pass filter on each input.
The recommended circuit configuration for driving the
differential inputs to achieve best performance is shown in
Figure 27. An RC low-pass filter is placed on both the analog
input pins. Recommended values for the resistors and capacitors
are 10 Ω and 220 pF, respectively. If possible, equalize the
source impedance on each analog input to minimize offset.
F
igure 27. RC Low-Pass Filter Input Network
The input filter configuration for the AD7405 is not limited to
the low-pass structure shown in Figure 27. The differential RC
filter configuration shown in Figure 28 also achieves excellent
performance. Recommended values for the resistors and
capacitor are 22 Ω and 47 pF, respectively.
F
igure 28. Differential RC Filter Input Network
Figure 29 compares the typical performance for the input filter
structures outlined in Figure 27 and Figure 28 for different
resistor and capacitor values.
F
igure 29. SNR vs. Decimation Rate for Different Filter Structures for Different
Resistor and Capacitor Values
DIGITAL FILTER
The output of the AD7405 is a continuous LVDS digital bit stream.
To reconstruct the original input signal information, this output
bit stream needs to be digitally filtered and decimated. A sinc
filter is recommended due to its simplicity. A sinc3 filter is
recommended because it is one order higher than that of the
AD7405 modulator, which is a second-order modulator. The type
of filter selected, the decimation rate, and the modulator clock used
determines the overall system resolution and throughput rate. The
higher the decimation rate, the greater the system accuracy, as
illustrated in Figure 30. However, there is a trade-off between
accuracy and throughput rate and, therefore, higher decimation
rates result in lower throughput solutions. Note that for a given
bandwidth requirement, a higher MCLKIN frequency can allow
higher decimation rates to be used, resulting in higher SNR
performance.
F
igure 30. SNR vs. Decimation Rate for Different Sinc Filter Orders
A sinc3 filter is recommended for use with the AD7405. This
filter can be implemented on a field programmable gate array
(FPGA) or a digital signal processor (DSP).
Equation 1 describes the transfer function of a sinc filter.
( )
( )
N
DR
Z
Z
DR
zH
−
−
=
−
−
1
1
11
)(
(1)
where DR is the decimation rate and N is the sinc filter order.
The throughput rate of the sinc filter is determined by the
modulator clock and the decimation rate selected.
DR
MCLK
Throughput =
(2)
where MCLK is the modulator clock frequency
As the decimation rate increases, the data output size from the
sinc filter increases. The output data size is expressed
in Equation 3. The 16 most significant bits are used to return a
16-bit result.
Data size = N × log
2
DR (3)
R
V
IN–
R
V
IN+
C
C
AD7405
12536-027
R
V
IN–
R
V
IN+
C
AD7405
12536-028
50
55
60
65
70
75
80
85
90
95
10 100 1000
SNR (dB)
DECIMATION RATE
LOW PASS, 10Ω, 220pF
DIFFERENTIAL, 22Ω, 47pF
DIFFERENTIAL, 22Ω, 10nF
f
IN
= 1kHz
12536-029
0
10
20
30
40
50
60
70
80
90
100
10 100 1000
SNR (dB)
DECIMATION RATE
SINC1
SINC2
SINC3
SINC4
f
IN
= 1kHz
12536-030
Rev. A | Page 16 of 20
Data Sheet AD7405
For a sinc3 filter, the −3 dB filter response point can be derived
from the filter transfer function, Equation 1, and is 0.262 times
the throughput rate. The filter characteristics for a third-order
sinc3 filter are summarized in Table 11.
Table 11. Sinc3 Filter Characteristics for 20 MHz MCLKIN
Decimation
Ratio (DR)
Throughput
Rate (kHz)
Output Data
Size (Bits)
Filter
Response (kHz)
32 625 15 163.7
64 312.5 18 81.8
128 156.2 21 40.9
256 78.1 24 20.4
512 39.1 27 10.2
The following Verilog code provides an example of a sinc3 filter
implementation on a Xilinx® Spartan®-6 FPGA. Note that the
data is read on the positive clock edge. It is recommended to
read in the data on the positive clock edge. The code is
configurable to accommodate decimation rates from 32 to 4096.
module dec256sinc24b
(
input mclk1, /* used to clk filter */
input reset, /* used to reset filter */
input mdata1, /* input data to be filtered
*/
output reg [15:0] DATA, /* filtered output
*/
output reg data_en,
input [15:0] dec_rate
);
/* Data is read on positive clk edge */
reg [36:0] ip_data1;
reg [36:0] acc1;
reg [36:0] acc2;
reg [36:0] acc3;
reg [36:0] acc3_d2;
reg [36:0] diff1;
reg [36:0] diff2;
reg [36:0] diff3;
reg [36:0] diff1_d;
reg [36:0] diff2_d;
reg [15:0] word_count;
reg word_clk;
reg enable;
/*Perform the Sinc action*/
always @ (mdata1)
if(mdata1==0)
ip_data1 <= 37'd0;
/* change 0 to a -1 for twos
complement */
else
ip_data1 <= 37'd1;
/*Accumulator (Integrator)
Perform the accumulation (IIR) at the speed
of the modulator.
Z = one sample delay MCLKOUT = modulators
conversion bit rate */
F
igure 31. Accumulator
always @ (negedge mclk1, posedge reset)
begin
if (reset)
begin
/* initialize acc registers on reset
*/
acc1 <= 37'd0;
acc2 <= 37'd0;
acc3 <= 37'd0;
end
else
begin
/*perform accumulation process */
acc1 <= acc1 + ip_data1;
acc2 <= acc2 + acc1;
acc3 <= acc3 + acc2;
end
end
/*decimation stage (MCLKOUT/WORD_CLK) */
always @ (posedge mclk1, posedge reset)
begin
if (reset)
word_count <= 16'd0;
else
begin
if ( word_count == dec_rate -
1 )
word_count <= 16'd0;
else
word_count <= word_count
+ 16'b1;
end
end
always @ ( posedge mclk1, posedge reset )
begin
if ( reset )
word_clk <= 1'b0;
else
begin
if ( word_count == dec_rate/2 -
1 )
word_clk <= 1'b1;
else if ( word_count ==
dec_rate - 1 )
word_clk <= 1'b0;
end
end
/*Differentiator (including decimation
stage)
Perform the differentiation stage (FIR) at a
lower speed.
MCLKIN
IP_DATA1
ACC1+
ACC2+
ACC3+
+
Z
+
Z
+
Z
12536-031
Rev. A | Page 17 of 20
P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21

AD7405BRIZ-RL7

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Buy AD7405BRIZ-RL7
Manufacturer:
Analog Devices Inc.
Description:
Analog to Digital Converters - ADC Iso-16Bit SigmaDelta ADC Ext Clk LVDS
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