AD7405 Data Sheet
Z = one sample delay WORD_CLK = output word
rate */
F
igure 32. Differentiator
always @ (posedge word_clk, posedge reset)
begin
if(reset)
begin
acc3_d2 <= 37'd0;
diff1_d <= 37'd0;
diff2_d <= 37'd0;
diff1 <= 37'd0;
diff2 <= 37'd0;
diff3 <= 37'd0;
end
else
begin
diff1 <= acc3 - acc3_d2;
diff2 <= diff1 - diff1_d;
diff3 <= diff2 - diff2_d;
acc3_d2 <= acc3;
diff1_d <= diff1;
diff2_d <= diff2;
end
end
/* Clock the Sinc output into an output
register
WORD_CLK = output word rate */
F
igure 33. Clocking Sinc3 Output into an Output Register
always @ ( posedge word_clk )
begin
case ( dec_rate )
16'd32:begin
DATA <= (diff3[15:0] ==
16'h8000) ? 16'hFFFF : {diff3[14:0], 1'b0};
end
16'd64:begin
DATA <= (diff3[18:2] ==
17'h10000) ? 16'hFFFF : diff3[17:2];
end
16'd128:begin
DATA <= (diff3[21:5] ==
17'h10000) ? 16'hFFFF : diff3[20:5];
end
16'd256:begin
DATA <= (diff3[24:8] ==
17'h10000) ? 16'hFFFF : diff3[23:8];
end
16'd512:begin
DATA <= (diff3[27:11] ==
17'h10000) ? 16'hFFFF : diff3[26:11];
end
16'd1024:begin
DATA <= (diff3[30:14] ==
17'h10000) ? 16'hFFFF : diff3[29:14];
end
16'd2048:begin
DATA <= (diff3[33:17] ==
17'h10000) ? 16'hFFFF : diff3[32:17];
end
16'd4096:begin
DATA <= (diff3[36:20] ==
17'h10000) ? 16'hFFFF : diff3[35:20];
end
default:begin
DATA <= (diff3[24:8] ==
17'h10000) ? 16'hFFFF : diff3[23:8];
end
endcase
end
/* Synchronize Data Output*/
always@ ( posedge mclk1, posedge reset )
begin
if ( reset )
begin
data_en <= 1'b0;
enable <= 1'b1;
end
else
begin
if ( (word_count == dec_rate/2
- 1) && enable )
begin
data_en <= 1'b1;
enable <= 1'b0;
end
else if ( (word_count ==
dec_rate - 1) && ~enable )
begin
data_en <= 1'b0;
enable <= 1'b1;
end
else
data_en <= 1'b0;
end
end
endmodule
WORD_CLK
ACC3
DIFF1
DIFF3
+
+
DIFF2
Z
–1
+
Z
–1
Z
–1
12536-032
WORD_CLK
DATA
DIFF3
12536-033
Rev. A | Page 18 of 20
Data Sheet AD7405
GROUNDING AND LAYOUT
It is recommended to decouple the V
DD1
supply with a 10 µF
capacitor in parallel with a 1 nF capacitor to GND
1
. Decouple
Pin 1 and Pin 7 individually. Decouple the V
DD2
supply with a
100 nF value to GND
2
. In applications involving high common-
mode transients, minimize board coupling across the isolation
barrier. Furthermore, design the board layout so that any
coupling that occurs equally affects all pins on a given
component side. Failure to ensure equal coupling can cause
voltage differentials between pins to exceed the absolute
maximum ratings of the device, thereby leading to latch-up or
permanent damage. Place any decoupling used as close to the
supply pins as possible.
Minimize series resistance in the analog inputs to avoid any
distortion effects, especially at high temperatures. If possible,
equalize the source impedance on each analog input to minimize
offset. To reduce offset drift, check for mismatch and thermocouple
effects on the analog input printed circuit board (PCB) tracks.
INSULATION LIFETIME
All insulation structures eventually break down when subjected
to voltage stress over a sufficiently long period. The rate of
insulation degradation is dependent on the characteristics of the
voltage waveform applied across the insulation. In addition to
the testing performed by the regulatory agencies, Analog
Devices carries out an extensive set of evaluations to determine
the lifetime of the insulation structure within the AD7405.
Analog Devices performs accelerated life testing using voltage
levels higher than the rated continuous working voltage.
Acceleration factors for several operating conditions are
determined. These factors allow calculation of the time to
failure at the actual working voltage. The values shown in Table 8
summarize the peak voltage for 20 years of service life for a
bipolar, ac operating condition and the maximum VDE
approved working voltages.
These tests subjected the AD7405 to continuous cross isolation
voltages. To accelerate the occurrence of failures, the selected
test voltages were values exceeding those of normal use. The
time to failure values of these units were recorded and used to
calculate the acceleration factors. These factors were then used
to calculate the time to failure under the normal operating
conditions. The values shown in Table 8 are the lesser of the
following two values:
The value that ensures at least a 20-year lifetime of
continuous use.
The maximum VDE approved working voltage.
Note that the lifetime of the AD7405 varies according to the
waveform type imposed across the isolation barrier. The
iCoupler insulation structure is stressed differently, depending
on whether the waveform is bipolar ac, unipolar ac, or dc.
Figure 34, Figure 35, and Figure 36 illustrate the different
isolation voltage waveforms.
F
igure 34. Bipolar AC Waveform, 50 Hz or 60 Hz
F
igure 35. Unipolar AC Waveform, 50 Hz or 60 Hz
F
igure 36. DC Waveform
0V
RATED PEAK VOLTAGE
12536-034
0V
RATED PEAK VOLTAGE
12536-035
0V
RATED PEAK VOLTAGE
12536-036
Rev. A | Page 19 of 20
AD7405 Data Sheet
OUTLINE DIMENSIONS
Fig
ure 37. 16-Lead Standard Small Outline Package, with Increased Creepage [SOIC_IC]
Wide Body
(RI-16-2)
Dimensions shown in millimeters
ORDERING GUIDE
Model
1
Temperature Range Package Description
Package
Option
AD7405BRIZ −40°C to +125°C 16-Lead Standard Small Outline Package, with Increased Creepage [SOIC_IC] RI-16-2
AD7405BRIZ-RL
−40°C to +125°C
16-Lead Standard Small Outline Package, with Increased Creepage [SOIC_IC]
RI-16-2
AD7405BRIZ-RL7 −40°C to +125°C 16-Lead Standard Small Outline Package, with Increased Creepage [SOIC_IC] RI-16-2
EVAL-AD7405FMCZ Evaluation Board
EVAL-SDP-CH1Z System Demonstration Platform
1
Z = RoHS Compliant Part.
11-15-2011-A
16
9
81
SEATING
PLANE
COPLANARITY
0.1
1.27 BSC
12.85
12.75
12.65
7.60
7.50
7.40
2.64
2.54
2.44
1.01
0.76
0.51
0.30
0.20
0.10
10.51
10.31
10.11
0.46
0.36
2.44
2.24
PIN 1
MARK
1.93 REF
0.32
0.23
0.71
0.50
0.31
45°
0.25 BSC
GAGE
PLANE
COMPLIANT TO JEDEC STANDARDS MS-013-AC
©2014 Analog Devices, Inc. All rights reserved. Trademarks and
registered trademarks are the property of their respective owners.
D12536-0-11/14(A)
Rev. A | Page 20 of 20

AD7405BRIZ

Mfr. #:
Manufacturer:
Analog Devices Inc.
Description:
Analog to Digital Converters - ADC ADC Iso 16Bit LVDS SigmaDelta Mod
Lifecycle:
New from this manufacturer.
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