Data Sheet AD7405
SPECIFICATIONS
V
DD1
= 4.5 V to 5.5 V, V
DD2
= 3 V to 5.5 V, V
IN+
= −250 mV to +250 mV, V
IN
= 0 V, T
A
= −40°C to +125°C, f
MCLKIN
1
= 5 MHz to 20 MHz, tested
with sinc3 filter, 256 decimation rate, as defined by Verilog code, unless otherwise noted. All voltages are relative to their respective ground.
Table 1.
Parameter Symbol Min Typ Max Unit Test Conditions/Comments
STATIC PERFORMANCE
Resolution
16 Bits Filter output truncated to 16 bits
Integral Nonlinearity
2
INL ±2 ±12 LSB
Differential Nonlinearity
2
DNL ±0.99 LSB Guaranteed no missing codes to 16 bits
Offset Error
2
±0.2 ±0.75 mV
Offset Drift vs. Temperature
3.8
µV/°C
1.3 3.1 µV/°C 0°C to 85°C
Offset Drift vs. V
DD1
50 µV/V
Gain Error
2
±0.2 ±0.8 % FSR f
MCLKIN
= 16 MHz
±0.2 ±0.8 % FSR f
MCLKIN
= 20 MHz, T
A
= −40°C to +85°C
±0.2 ±1.2 % FSR f
MCLKIN
= 20 MHz
Gain Error Drift vs. Temperature 65 95 ppm/°C
40 60 µV/°C
Gain Error Drift vs. V
DD1
±0.6 mV/V
ANALOG INPUT
Input Voltage Range −320 +320 mV Full-scale range
−250 +250 mV For specified performance
Input Common-Mode Voltage Range 200 to +300 mV
Dynamic Input Current ±45 ±50 µA V
IN+
= ±250 mV, V
IN
− = 0 V
µA
V
IN+
= 0 V, V
IN−
= 0 V
DC Leakage Current ±0.01 ±0.6 µA
Input Capacitance 14 pF
DYNAMIC SPECIFICATIONS V
IN+
= 1 kHz
Signal-to-Noise-and-Distortion Ratio
2
SINAD 81 87 dB
83 87 dB −40°C to +85°C
Signal-to-Noise Ratio
2
SNR 86 88 dB
Total Harmonic Distortion
2
THD −96 dB
Peak Harmonic or Spurious Noise
2
SFDR 97 dB
Effective Number of Bits
2
ENOB
13.1
Bits
13.4 14.2 Bits −40°C to +85°C
Noise Free Code Resolution
2
14 Bits
ISOLATION TRANSIENT IMMUNITY
2
25 30 kV/µs
LVDS I/O (ANSI-644)
Differential Output Voltage V
OD
247 360 454 mV R
L
= 100 Ω
Common-Mode Output Voltage V
OCM
1125 1260 1375 mV RL = 100 Ω
Differential Input Voltage V
ID
150 650 mV
Common-Mode Input Voltage V
ICM
800 1575 mV
POWER REQUIREMENTS
V
DD1
4.5 5.5 V
V
DD2
3
5.5
V
I
DD1
30 36 mA V
DD1
= 5.5 V
I
DD2
18 22 mA V
DD2
= 5.5 V
13 15 mA V
DD2
= 3.3 V
Power Dissipation 264 319 mW V
DD1
= V
DD2
= 5.5 V
208 248 mW V
DD1
= 5.5 V, V
DD2
= 3.3 V
1
For f
MCLKIN
> 16 MHz, mark space ratio is 48/52 to 52/48, and VDD1 = 5 V ± 5%.
2
See the Terminology section.
Rev. A | Page 3 of 20
AD7405 Data Sheet
TIMING SPECIFICATIONS
V
DD1
= 4.5 V to 5.5 V, V
DD2
= 3 V to 5.5 V, T
A
= −40°C to +125°C, unless otherwise noted. Sample tested during initial release to ensure
compliance. It is recommended to read the MDAT signal on the MCLKIN+ rising edge.
Table
2.
Parameter
1
Limit at T
MIN
, T
MAX
Unit Description
f
MCLKIN
5 MHz minimum Master clock input frequency
20 MHz maximum
t
1
Data access time after MCLKIN+ rising edge
30 ns maximum V
DD2
= 4.5 V to 5.5 V
40 ns maximum V
DD2
= 3 V to 3.6 V
t
2
Data hold time after MCLKIN+ rising edge
10 ns minimum V
DD2
= 4.5 V to 5.5 V
10 ns minimum V
DD2
= 3 V to 3.6V
t
3
Master clock low time
0.45 × t
MCLKIN
ns minimum f
MCLKIN
≤ 16 MHz
0.48 × t
MCLKIN
ns minimum
16 MHz < f
MCLKIN
≤ 20 MHz
t
4
Master clock high time
0.45 × t
MCLKIN
ns minimum f
MCLKIN
≤ 16 MHz
0.48 × t
MCLKIN
ns minimum 16 MHz < f
MCLKI
N ≤ 20 MHz
1
Sample tested during initial release to ensure compliance.
Fig
ure 2. Data Timing
MCLKIN+
MDAT+
t
1
t
2
t
3
t
4
MCLKIN–
MDAT
12536-002
Rev. A | Page 4 of 20
Data Sheet AD7405
PACKAGE CHARACTERISTICS
Table 3.
Parameter Symbol Min Typ Max Unit Test Conditions/Comments
Resistance (Input to Output)
1
R
I-O
10
12
Ω
Capacitance (Input to Output)
1
C
I-O
2.2 pF f = 1 MHz
IC Junction to Ambient Thermal Resistance θ
JA
45 °C/W Thermocouple located at center of package underside,
test conducted on 4-layer board with thin traces
1
The device is considered a 2-terminal device: Pin 1 to Pin 8 are shorted together, and Pin 9 to Pin 16 are shorted together.
INSULATION AND SAFETY RELATED SPECIFICATIONS
Table 4.
Parameter Symbol Value Unit Test Conditions/Comments
Input to Output Momentary Withstand Voltage V
ISO
5000 min V 1 minute duration
Minimum External Air Gap (Clearance) L(I01) 8.3 min
1, 2
mm Measured from input terminals to output
terminals, shortest distance through air
Minimum External Tracking (Creepage) L(I02) 8.3 min
1
mm Measured from input terminals to output
terminals, shortest distance path along body
Minimum Internal Gap (Internal Clearance) 0.034 min mm Distance through insulation
Tracking Resistance (Comparative Tracking Index) CTI >400 V DIN IEC 112/VDE 0303 Part 1
3
Isolation Group II Material Group (DIN VDE 0110, 1/89, Table I)
3
1
In accordance with IEC 60950-1 guidelines for the measurement of creepage and clearance distances for a pollution degree of 2 and altitudes ≤2000 meters.
2
Consideration must be given to pad layout to ensure the minimum required distance for clearance is maintained.
3
CSA CTI rating for the AD7405 is >600 V and a Material Group I isolation group.
REGULATORY INFORMATION
Table 5.
UL
1
CSA VDE
2
Recognized under 1577
Component Recognition
Program
1
Approved under CSA Component Acceptance Notice 5A Certified according to DIN V VDE V 0884-10
(VDE V 0884-10):2006-12
2
5000 V rms Isolation Voltage
Single Protection
Basic insulation per CSA 60950-1-07 and IEC 60950-1,
830 V rms (1173 V
PEAK
) maximum working voltage
3
Reinforced insulation per DIN V VDE V 0884-10
(VDE V 0884-10):2006-12, 1250 V
PEAK
Reinforced insulation per CSA 60950-1-07 and
IEC 60950-1, 415 V rms (586 V
PEAK
) maximum working
voltage
3
Reinforced insulation per IEC 60601-1, 250 V rms
(353 V
PEAK
) maximum working voltage
File E214100 File 205078 File 2471900-4880-0001
1
In accordance with UL 1577, each AD7405 is proof tested by applying an insulation test voltage ≥ 6000 V rms for 1 second (current leakage detection limit = 15 µA).
2
In accordance with DIN V VDE V 0884-10, each AD7405 is proof tested by applying an insulation test voltage of ≥ 2344 V
PEAK
for 1 second (partial discharge detection limit = 5 pC).
3
Rating is calculated for a pollution degree of 2 and a Material Group III. The AD7405 RI-16-2 package material is rated by CSA to a CTI of >600 V and, therefore,
Material Group I.
Rev. A | Page 5 of 20

AD7405BRIZ

Mfr. #:
Manufacturer:
Analog Devices Inc.
Description:
Analog to Digital Converters - ADC ADC Iso 16Bit LVDS SigmaDelta Mod
Lifecycle:
New from this manufacturer.
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