PIC12LF1552
DS41642A-page 24 Preliminary 2012 Microchip Technology Inc.
8.0 ELECTRICAL SPECIFICATIONS
Refer to the device specific data sheet for absolute
maximum ratings.
TABLE 8-1: AC/DC CHARACTERISTICS TIMING REQUIREMENTS FOR PROGRAM/VERIFY MODE
AC/DC CHARACTERISTICS
Standard Operating Conditions
Production tested at 25°C
Sym. Characteristics Min. Typ. Max. Units Conditions/Comments
Supply Voltages and Currents
V
DD
VDD Read/Write and Row Erase operations VDDMIN —VDDMAX V
Bulk Erase operations 2.7 — V
DDMAX V
I
DDI Current on VDD, Idle — — 1.0 mA
I
DDP Current on VDD, Programming — — 3.0 mA
I
PP
VPP
Current on MCLR/VPP ——600A
V
IHH
High voltage on MCLR/VPP for
Program/Verify mode entry
8.0 — 9.0 V
T
VHHR
MCLR rise time (VIL to VIHH) for
Program/Verify mode entry
——1.0s
I/O pins
V
IH (ICSPCLK, ICSPDAT, MCLR/VPP) input high level 0.8 VDD ——V
V
IL (ICSPCLK, ICSPDAT, MCLR/VPP) input low level — — 0.2 VDD V
V
OH
ICSPDAT output high level
V
DD-0.7 — — V
I
OH = 3.5 mA, VDD = 5V
I
OH = 3 mA, VDD = 3.3V
I
OH = 2 mA, VDD = 1.8V
V
OL
ICSPDAT output low level
——0.6V
IOH = 8 mA, VDD = 5V
I
OH = 6 mA, VDD = 3.3V
I
OH = 3 mA, VDD = 1.8V
Programming Mode Entry and Exit
T
ENTS
Programing mode entry setup time: ICSPCLK,
ICSPDAT setup time before V
DD or MCLR
100 — — ns
T
ENTH
Programing mode entry hold time: ICSPCLK,
ICSPDAT hold time after V
DD or MCLR
250 — — s
Serial Program/Verify
T
CKL Clock Low Pulse Width 100 — — ns
T
CKH Clock High Pulse Width 100 — — ns
T
DS Data in setup time before clock 100 — — ns
T
DH Data in hold time after clock 100 — — ns
T
CO
Clock to data out valid (during a
Read Data command)
0—80ns
T
LZD
Clock to data low-impedance (during a
Read Data command)
0—80ns
T
HZD
Clock to data high-impedance (during a
Read Data command)
0—80ns
T
DLY
Data input not driven to next clock input (delay required
between command/data or command/command)
1.0 — — s
T
ERAB Bulk Erase cycle time — — 5 ms
T
ERAR Row Erase cycle time — — 2.5 ms
T
PINT
Internally timed programming operation time —
—
—
—
2.5
5
ms
ms
Program memory
Configuration Words
T
PEXT Externally timed programming pulse 1.0 — 2.1 ms Note 1
T
DIS
Time delay from program to compare
(HV discharge time)
300 — — s
T
EXIT Time delay when exiting Program/Verify mode 1 — — s
Note 1: Externally timed writes are not supported for Configuration and Calibration bits.