ADG5412W Data Sheet
TERMINOLOGY
I
DD
I
DD
represents the positive supply current.
I
SS
I
SS
represents the negative supply current.
V
D
, V
S
V
D
and V
S
represent the analog voltage on Terminal D and
Terminal S, respectively.
R
ON
R
ON
represents the ohmic resistance between Terminal D and
Terminal S.
∆R
ON
∆R
ON
represents the difference between the R
ON
of any two
channels.
R
FLAT (ON)
Flatness that is defined as the difference between the maximum
and minimum value of on resistance measured over the specified
analog signal range is represented by R
FLAT (ON)
.
I
S
(Off)
I
S
(Off) is the source leakage current with the switch off.
I
D
(Off)
I
D
(Off) is the drain leakage current with the switch off.
I
D
(On), I
S
(On)
I
D
(On) and I
S
(On) represent the channel leakage currents with
the switch on.
V
INL
V
INL
is the maximum input voltage for Logic 0.
V
INH
V
INH
is the minimum input voltage for Logic 1.
I
INL
, I
INH
I
INL
and I
INH
represent the low and high input currents of the
digital inputs.
C
D
(Off)
C
D
(Off) represents the off switch drain capacitance, which is
measured with reference to ground.
C
S
(Off)
C
S
(Off) represents the off switch source capacitance, which is
measured with reference to ground.
C
D
(On), C
S
(On)
C
D
(On) and C
S
(On) represent on switch capacitances, which
are measured with reference to ground.
C
IN
C
IN
is the digital input capacitance.
t
ON
t
ON
represents the delay between applying the digital control
input and the output switching on.
t
OFF
t
OFF
represents the delay between applying the digital control
input and the output switching off.
t
D
t
D
represents the off time measured between the 80% point of
both switches when switching from one address state to
another.
Off Isolation
Off isolation is a measure of unwanted signal coupling through
an off switch.
Charge Injection
Charge injection is a measure of the glitch impulse transferred
from the digital input to the analog output during switching.
Crosstalk
Crosstalk is a measure of unwanted signal that is coupled
through from one channel to another as a result of parasitic
capacitance.
Bandwidth
Bandwidth is the frequency at which the output is attenuated
by 3 dB.
On Response
On response is the frequency response of the on switch.
Insertion Loss
Insertion loss is the loss due to the on resistance of the switch.
Total Harmonic Distortion + Noise (THD + N)
The ratio of the harmonic amplitude plus noise of the signal to
the fundamental is represented by THD + N.
AC Power Supply Rejection Ratio (ACPSRR)
ACPSRR is the ratio of the amplitude of signal on the output to the
amplitude of the modulation. This is a measure of the ability of
the part to avoid coupling noise and spurious signals that appear
on the supply voltage pin to the output of the switch. The dc voltage
on the device is modulated by a sine wave of 0.62 V p-p.
Rev. A | Page 16 of 20
Data Sheet ADG5412W
APPLICATIONS INFORMATION
The ADG54xx family of switches and multiplexers provide a
robust solution for instrumentation, industrial, automotive,
aerospace, and other harsh environments that are prone to
latch-up, which is an undesirable high current state that can
lead to device failure and persists until the power supply is
turned off. The ADG5412W high voltage switches allow single-
supply operation from 9 V to 40 V and dual-supply operation
from ±9 V to ±22 V. T h e ADG5412W (as well as other select
devices within the same family) achieve an 8 kV human body
model ESD rating, which provides a robust solution eliminating
the need for separate protect circuitry designs in some
applications.
TRENCH ISOLATION
In the ADG5412W, an insulating oxide layer (trench) is placed
between the NMOS and the PMOS transistors of each CMOS
switch. Parasitic junctions, which occur between the transistors
in junction isolated switches, are eliminated, and the result is a
completely latch-up proof switch.
In junction isolation, the N and P wells of the PMOS and NMOS
transistors form a diode that is reverse-biased under normal
operation. However, during overvoltage conditions, this diode
can become forward-biased. A silicon controlled rectifier (SCR)
type circuit is formed by the two transistors causing a significant
amplification of the current that, in turn, leads to latch-up. With
trench isolation, this diode is removed, and the result is a latch-
up proof switch.
Figure 32. Trench Isolation
NMOS PMOS
P-WELL N-WELL
BURIED OXIDE LAYER
HANDLE WAFER
TRENCH
11695-022
Rev. A | Page 17 of 20
ADG5412W Data Sheet
OUTLINE DIMENSIONS
Figure 33. 16-Lead Thin Shrink Small Outline Package [TSSOP]
(RU-16)
Dimensions shown in millimeters
Figure 34. 16-Lead Lead Frame Chip Scale Package [LFCSP_WQ]
4 mm × 4 mm Body, Very Very Thin Quad
(CP-16-17)
Dimensions shown in millimeters
ORDERING GUIDE
Model
1, 2
Temperature Range Package Description Package Option
ADG5412WBRUZ-REEL7 −40°C to +125°C 16-Lead Thin Shrink Small Outline Package [TSSOP] RU-16
ADG5412WBCPZ-REEL7 −40°C to +125°C 16-Lead Lead Frame Chip Scale Package [LFCSP_WQ] CP-16-17
1
Z = RoHS Compliant Part.
2
W = Qualified for Automotive Applications.
AUTOMOTIVE PRODUCTS
The ADG5412W models are available with controlled manufacturing to support the quality and reliability requirements of automotive
applications. Note that these automotive models may have specifications that differ from the commercial models; therefore, designers
should review the Specifications section of this data sheet carefully. Only the automotive grade products shown are available for use in
automotive applications. Contact your local Analog Devices account representative for specific product ordering information and to
obtain the specific Automotive Reliability reports for these models.
16
9
81
PIN 1
SEATING
PLANE
4.50
4.40
4.30
6.40
BSC
5.10
5.00
4.90
0.65
BSC
0.15
0.05
1.20
MAX
0.20
0.09
0.75
0.60
0.45
0.30
0.19
COPLANARITY
0.10
COMPLIANT TO JEDEC STANDARDS MO-153-AB
2.70
2.60 SQ
2.50
COMPLIANT
TO
JEDEC STANDARDS MO-220-WGGC.
1
0.65
BSC
BOTTOMVIEWTOP VIEW
16
5
8
9
12
13
4
EXPOSED
PAD
PIN 1
INDICATOR
4.10
4.00 SQ
3.90
0.45
0.40
0.35
SEATING
PLANE
0.80
0.75
0.70
0.05 MAX
0.02 NOM
0.20 REF
0.20 MIN
COPLANARITY
0.08
PIN 1
INDICATOR
0.35
0.30
0.25
FOR PROPER CONNECTION OF
THE EXPOSED PAD, REFER TO
THE PIN CONFIGURATION AND
FUNCTION DESCRIPTIONS
SECTION OF THIS DATA SHEET.
08-16-2010-C
Rev. A | Page 18 of 20

ADG5412WBCPZ-REEL7

Mfr. #:
Manufacturer:
Analog Devices Inc.
Description:
Analog Switch ICs 20V Latchup Protectd of quad SPST
Lifecycle:
New from this manufacturer.
Delivery:
DHL FedEx Ups TNT EMS
Payment:
T/T Paypal Visa MoneyGram Western Union

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