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MT41K512M16TNA-125:E

P1-P3P4-P6P7-P9P10-P12P13-P13
Figure 3: Temperature Test Point Location
Test point
Length (L)
Width (W)
0.5 (W)
0.5 (L)
Table 6: Thermal Impedance
Die Rev Package Substrate
ΘJA (°C/W)
Airflow =
0m/s
ΘJA (°C/W)
Airflow =
1m/s
ΘJA (°C/W)
Airflow =
2m/s ΘJB (°C/W) ΘJC (°C/W) Notes
E 96-ball Low con-
ductivity
48.0 36.4 31.9 n/a 1.8 1
High con-
ductivity
28.6 23.4 21.6 16.5 n/a
Note:
1. Thermal resistance data is based on a number of samples from multiple lots and should
be viewed as a typical number.
8Gb: x16 TwinDie DDR3L SDRAM
Electrical Specifications
PDF: 09005aef84ccb467
DDR3L_8Gb_x16_2CS_TwinDie.pdf - Rev. D 10/13 EN
10
Micron Technology, Inc. reserves the right to change products or specifications without notice.
© 2012 Micron Technology, Inc. All rights reserved.
Electrical Specifications – I
CDD
Parameters
Table 7: DDR3L I
CDD
Specifications and Conditions (Die Revision E)
Combined
Symbol
Individual
Die Status
Bus
Width -187E -15E -125 -107 Units
I
CDD0
I
CDD0
=
I
DD0
+ I
DD2P0
+ 5
x16 78 81 89 96 mA
I
CDD1
I
CDD1
=
I
DD1
+ I
DD2P0
+ 5
x16 103 107 110 114 mA
I
CDD2P0
(slow exit) I
CDD2P0
=
I
DD2P0
+ I
DD2P0
x16 36 36 36 36 mA
I
CDD2P1
(fast exit) I
CDD2P1
=
I
DD2P1
+ I
DD2P0
x16 44 46 50 55 mA
I
CDD2Q
I
CDD2Q
=
I
DD2Q
+ I
DD2P0
x16 45 46 50 53 mA
I
CDD2N
I
CDD2N
=
I
DD2N
+ I
DD2P0
x16 46 47 50 53 mA
I
CDD2N T
I
CDD2NT
=
I
DD2NT
+ I
DD2P0
x16 53 57 60 63 mA
I
CDD3P
I
CDD3P
= I
DD3P
+ I
DD2P0
x16 50 53 56 59 mA
I
CDD3N
I
CDD3N
=
I
DD3N
+ I
DD2P0
x16 59 63 65 67 mA
I
CDD4R
I
CDD4R
=
I
DD4R
+ I
DD2P0
+ 5
x16 208 225 258 275 mA
I
CDD4W
I
CDD4W
=
I
DD4W
+ I
DD2P0
+ 5
x16 160 175 194 213 mA
I
CDD5B
I
CDD5B
=
I
DD5B
+ I
DD2P0
x16 242 246 253 257 mA
I
CDD6
(room temperature)
I
CDD6
=
I
DD6
+ I
DD6
x16 40 40 40 40 mA
I
CDD6ET
(extended tempera-
ture)
I
CDD6ET
=
I
DD6ET
+ I
DD6ET
x16 50 50 50 50 mA
I
CDD7
I
CDD7
=
I
DD7
+ I
DD2P0
+ 5
x16 221 240 266 297 mA
I
CDD8
I
CDD8
= 2 × I
DD2P0
+ 4 x16 40 40 40 40 mA
Note:
1. I
CDD
values reflect the combined current of both individual die. I
DDx
represents individu-
al die values.
8Gb: x16 TwinDie DDR3L SDRAM
Electrical Specifications – I
CDD
Parameters
PDF: 09005aef84ccb467
DDR3L_8Gb_x16_2CS_TwinDie.pdf - Rev. D 10/13 EN
11
Micron Technology, Inc. reserves the right to change products or specifications without notice.
© 2012 Micron Technology, Inc. All rights reserved.
Package Dimensions
Figure 4: 96-Ball FBGA – Die Revision E (Package Code TNA)
Seating plane
0.12 A
Ball A1 ID
(covered by SR)
Ball A1 ID
0.25 MIN
1.1 ±0.1
6.4 CTR
10 ±0.1
0.8 TYP
12 CTR
14 ±0.1
96X Ø0.45
Dimensions
apply to solder
balls post- reflow
on Ø0.33 NSMD
ball pads.
0.8 TYP
123789
A
B
C
D
E
F
G
H
J
K
L
M
N
P
R
T
A
Notes:
1. All dimensions are in millimeters.
2. Solder ball material: SAC305 (96.5% Sn, 3% Ag, 0.5% Cu).
8Gb: x16 TwinDie DDR3L SDRAM
Package Dimensions
PDF: 09005aef84ccb467
DDR3L_8Gb_x16_2CS_TwinDie.pdf - Rev. D 10/13 EN
12
Micron Technology, Inc. reserves the right to change products or specifications without notice.
© 2012 Micron Technology, Inc. All rights reserved.
P1-P3P4-P6P7-P9P10-P12P13-P13

MT41K512M16TNA-125:E

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Manufacturer:
Micron
Description:
IC DRAM 8G PARALLEL 96FBGA
Lifecycle:
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