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LTC4268IDKD-1

P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21P22-P24P25-P27P28-P30P31-P33P34-P36P37-P39P40-P42P43-P45P46-P46
42681fc
LTC4268-1
37
applicaTions inForMaTion
max 100mV rating because of the minimum switch on
time blanking. If the voltage on V
SENSE
exceeds 205mV
after the minimum turn-on time, the SFST capacitor is
discharged, causing the discharge of the V
CMP
capacitor.
This then reduces the peak current on the next cycle and
will reduce overall stress in the primary switch.
Short-Circuit Conditions
Loss of current limit is possible under certain conditions
such as an output short circuit. If the duty cycle exhibited
by the minimum on time is greater than the ratio of
secondary winding voltage (referred-to-primary) divided
by input voltage, then peak current is not controlled at
the nominal value. It ratchets up cycle-by-cycle to some
higher level. Expressed mathematically, the requirement
to maintain short-circuit control is
DC
MIN
= t
ON(MIN)
• f
OSC
<
I
SC
• R
SEC
+ R
DS(ON)
( )
V
IN
• N
SP
where:
t
ON(MIN)
is the primary side switch minimum on-time
I
SC
is the short-circuit output current
N
SP
is the secondary-to-primary turns ratio (N
SEC
/N
PRI
)
(Other variables as previously defined)
Trouble is typically encountered only in applications with a
relatively high product of input voltage times secondary to
primary turns ratio and/or a relatively long minimum switch
on time. Additionally, several real world effects such as
transformer leakage inductance, AC winding losses, and
output switch voltage drop combine to make this simple
theoretical calculation a conservative estimate. Prudent
design evaluates the switcher for short-circuit protection
and adds any additional circuitry to prevent destruction
for these losses.
Output Voltage Error Sources
The LTC4268-1’s feedback sensing introduces additional
minor sources of errors. The following is a summary list.
• The internal bandgap voltage reference sets the reference
voltage for the feedback amplifier. The specifications
detail its variation.
• The external feedback resistive divider ratio directly
affects regulated voltage. Use 1% components.
• Leakage inductance on the transformer secondary
reduces the effective secondary-to-feedback winding
turns ratio (NS/NF) from its ideal value. This increases
the output voltage target by a similar percentage. Since
secondary
leakage inductance is constant from part to
part
(within a tolerance) adjust the feedback resistor
ratio to compensate.
• The transformer secondary current flows through the
impedances of the winding resistance, synchronous
MOSFET R
DS(ON)
and output capacitor ESR. The DC
equivalent current for these errors is higher than the
load current because conduction occurs only during
the converter’s “off” time. So divide the load current
by (1 – DC).
If the output load current is relatively constant, the feedback
resistive divider is used to compensate for these losses.
Otherwise, use the LTC4268-1 load compensation circuitry.
(See Load Compensation.) If multiple output windings are
used, the flyback winding will have a signal that represents
an amalgamation of all these windings impedances. Take
care that you examine worst-case loading conditions when
tweaking the voltages.
LTC4268-1
38
42681fc
Power MOSFET Selection
The power MOSFETs are selected primarily on the criteria of
“on” resistance R
DS(ON)
, input capacitance, drain-to-source
breakdown voltage (BV
DSS
), maximum gate voltage (V
GS
)
and maximum drain current (ID
(MAX)
).
For the primary-side power MOSFET, the peak current is:
I
PK(PRI)
=
P
IN
V
IN(MIN)
• DC
MAX
• 1+
X
MIN
2
where X
MIN
is peak-to-peak current ratio as defined
earlier. For each secondary-side power MOSFET, the peak
current is:
I
PK(SEC)
=
I
OUT
1−DC
MAX
• 1+
X
MIN
2
Select a primary-side power MOSFET with a BV
DSS
greater
than:
BV
DSS
≥I
PK
L
LKG
C
P
+ V
IN(MAX)
+
V
OUT(MAX)
N
SP
where N
SP
reflects the turns ratio of that secondary-to
primary winding. L
LKG
is the primary-side leakage induc-
tance and C
P
is the primary-side capacitance (mostly from
the drain capacitance (C
OSS
) of the primary-side power
MOSFET). A snubber may be added to reduce the leakage
inductance as discussed.
For each secondary-side power MOSFET, the BV
DSS
should
be greater than:
BV
DSS
≥ V
OUT
+ V
IN(MAX)
• N
SP
applicaTions inForMaTion
Choose the primary side MOSFET R
DS(ON)
at the nominal
gate drive voltage (7.5V). The secondary side MOSFET
gate drive voltage depends on the gate drive method.
Primary side power MOSFET RMS current is given by:
I
RMS(PRI)
=
P
IN
V
IN(MIN)
DC
MAX
For each secondary-side power MOSFET RMS current is
given by:
I
RMS(SEC)
=
I
OUT
1−DC
MAX
Calculate MOSFET power dissipation next. Because the
primary-side power MOSFET operates at high V
DS
, a
transition power loss term is included for accuracy. C
MILLER
is the most critical parameter in determining the transition
loss, but is not directly specified on the data sheets.
C
MILLER
is calculated from the gate charge curve included
on most MOSFET data sheets (Figure 17).
The flat portion of the curve is the result of the Miller
(gate-to-drain) capacitance as the drain voltage drops.
The Miller capacitance is computed as:
C
MILLER
=
Q
B
−Q
A
V
DS
The curve is done for a given V
DS
. The Miller capacitance
for different V
DS
voltages are estimated by multiplying the
computed C
MILLER
by the ratio of the application V
DS
to
the curve specified V
DS
.
Q
A
V
GS
a b
42681 F18
Q
B
MILLER EFFECT
GATE CHARGE (Q
G
)
Figure 18. Gate Charge Curve
42681fc
LTC4268-1
39
With C
MILLER
determined, calculate the primary-side power
MOSFET power dissipation:
P
D(PRI)
=I
RMS(PRI)
2
• R
DS(ON)
1+ d
( )
+
V
IN(MAX)
•
P
IN(MAX)
DC
MIN
• R
DR
•
C
MILLER
V
GATE(MAX)
− V
TH
• f
OSC
where:
R
DR
is the gate driver resistance (≈10W)
V
TH
is the MOSFET gate threshold voltage
f
OSC
is the operating frequency
V
GATE(MAX)
= 7.5V for this part
(1 + d) is generally given for a MOSFET in the form of a
normalized R
DS(ON)
vs temperature curve. If you don’t have
a curve, use d = 0.005/°C • DT for low voltage MOSFETs.
The secondary-side power MOSFETs typically operate
at substantially lower V
DS
, so you can neglect transition
losses. The dissipation is calculated using:
P
DIS(SEC)
= I
RMS(SEC)
2
• R
DS(ON)
(1 + d)
With power dissipation known, the MOSFETs’ junction
temperatures are obtained from the equation:
T
J
= T
A
+ P
DIS
• θ
JA
where T
A
is the ambient temperature and θ
JA
is the MOSFET
junction to ambient thermal resistance.
Once you have T
J
iterate your calculations recomputing
d and power dissipations until convergence.
Gate Drive Node Consideration
The PG and SG gate drivers are strong drives to minimize
gate drive rise and fall times. This improves efficiency
but the high frequency components of these signals can
cause problems. Keep the traces short and wide to reduce
parasitic inductance.
The parasitic inductance creates an
LC tank with the
MOSFET
gate capacitance. In less than ideal layouts, a
series resistance of 5W or more may help to dampen the
ringing at the expense of slightly slower rise and fall times
and poorer efficiency.
The LTC4268-1 gate drives will clamp the max gate voltage
to roughly 7.5V, so you can safely use MOSFETs with
maximum V
GS
of 10V and larger.
Synchronous Gate Drive
There are several different ways to drive the synchronous
gate MOSFET. Full converter isolation requires the synchro-
nous gate drive to be isolated. This is usually accomplished
by way of a pulse transformer. Usually the pulse driver is
used to drive a buffer on the secondary as shown in the
application on the front page of this data sheet.
However, other schemes are possible. There are gate drivers
and secondary side synchronous controllers available that
provide the buffer function as well as additional features.
Capacitor Selection
In a flyback converter, the input and output current flows
in pulses, placing severe demands on the input and output
filter capacitors. The input and output filter capacitors are
selected based on RMS current ratings and ripple voltage.
Select an input capacitor with a ripple current rating
greater than:
I
RMS(PRI)
=
P
IN
V
IN(MIN)
1−DC
MAX
DC
MAX
Continuing the example:
I
RMS(PRI)
=
29.5W
41V
1− 49.4%
49.4%
= 0.728A
Keep input capacitor series resistance (ESR) and
inductance (ESL) small, as they affect electromagnetic
interference suppression. In some instances, high ESR can
also produce stability problems because flyback converters
exhibit a negative input resistance characteristic. Refer
to Application Note 19 for more information. The output
capacitor is sized to handle the ripple current and to ensure
acceptable output voltage ripple.
applicaTions inForMaTion
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LTC4268IDKD-1

Mfr. #:
Buy LTC4268IDKD-1
Manufacturer:
Analog Devices / Linear Technology
Description:
Power Switch ICs - POE / LAN LTC4268-1 - High Power PD with Synchronous NoOpto Flyback Controller
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