LVDS, 1:4 CLOCK BUFFER TERABUFFER™ 3 Rev A 5/13/15
5T9304 DATA SHEET
Table 1. Pin Descriptions
NOTES:
1. Inputs are capable of translating the following interface standards:
Single-ended 3.3V and 2.5V LVTTL levels
Differential HSTL and eHSTL levels
Differential LVEPECL (2.5V) and LVPECL (3.3V) levels
Differential LVDS levels
Differential CML levels
2. Because the gate controls are asynchronous, runt pulses are possible. It is the user's responsibility to either time the gate control
signals to minimize the possibility of runt pulses or be able to tolerate them in down stream circuitry.
3. It is recommended that the outputs be disabled before entering power-down mode. It is also recommended that the outputs remain
disabled until the device completes power-up after asserting PD
.
4. The user must take precautions with any differential input interface standard being used in order to prevent instability when there is
no input signal.
Table 2. Pin Characteristics (TA = +25°C, F = 1.0MHz)
)
NOTE: This parameter is measured at characterization but not tested.
Number Name Type Description
1, 12, 22 GND Power Power supply return for all power.
2PDInput LVTTL
Power-down control. Shuts off entire chip. If LOW, the device goes into low
power mode. Inputs and outputs are disabled. Both Qx and Qx outputs will
pull to V
DD. Set HIGH for normal operation.
(3)
3 RESERVED Reserved Reserved pin.
4, 9, 16, 21 V
DD
Power Power supply for the device core and inputs.
5, 7,
18, 20
Q1, Q2,
Q4, Q3
Output LVDS Complementary differential clock outputs.
6, 8,
17, 19
Q1, Q2,
Q4, Q3
Output LVDS Differential clock outputs.
10 SEL Input LVTTL
Reference clock select. When LOW, selects A2 and A2
. When HIGH,
selects A1 and A1.
11 G Input LVTTL
Gate control for differential outputs Q1 and Q1 through Q4 and Q4. When G
is LOW, the differential outputs are active. When G is HIGH, the differential
outputs are asynchronously driven to the level designated by GL
(2)
.
13, 24 A1, A2 Input Adjustable
(1, 4)
Clock input. A[1:2] is the "true" side of the differential clock input.
14, 23 A
1, A2 Input Adjustable
(1, 4)
Complementary clock inputs. A[1:2] is the complementary side of A[1:2].
For LVTTL single-ended operation, A[1:2] should be set to the desired
toggle voltage for A[1:2]:
3.3V LVTTL V
REF = 1650mV
2.5V LVTTL VREF = 1250mV
15 GL Input LVTTL
Specifies output disable level. If HIGH, Qx outputs disable HIGH and Qx
outputs disable LOW. If LOW, Qx outputs disable LOW and Qx outputs
disable HIGH.
Symbol Parameter Test Conditions Minimum Typical Maximum Units
C
IN
Input Capacitance 3pF
