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5T9304PGG

P1-P3P4-P6P7-P9P10-P12P13-P15P16-P16
Rev A 5/13/15 10 LVDS, 1:4 CLOCK BUFFER TERABUFFER™
5T9304 DATA SHEET
Power Down Timing
NOTE 1: It is recommended that outputs be disabled before entering power-down mode. It is also recommended that the outputs remain
disabled until the device completes power-up after asserting PD.
NOTE 2: The Power Down Timing diagram assumes that GL is HIGH.
NOTE 3: It should be noted that during power-down mode, the outputs are both pulled to V
DD
. In the Power Down Timing diagram this is
shown when Qn/Qn goes to V
DIF
= 0.
LVDS, 1:4 CLOCK BUFFER TERABUFFER™ 11 Rev A 5/13/15
5T9304 DATA SHEET
Test Circuit for Differential Input
Table 6A. Differential Input Test Conditions
Symbol V
DD
= 2.5V ± 0.2V Unit
V
THI
Crossing of A and A V
VDD/2
D.U.T.
A
A
Pulse
Generator
~50Ω
Transmission Line
~50Ω
Transmission Line
VIN
VIN
-VDD/2
Scope
50Ω
50Ω
Rev A 5/13/15 12 LVDS, 1:4 CLOCK BUFFER TERABUFFER™
5T9304 DATA SHEET
Test Circuit for DC Outputs and Power Down Tests
Test Circuit for Propagation, Skew, and Gate Enable/Disable Timing
Table 6B. Differential Input Test Conditions
NOTE 1: Specifications only apply to “Normal Operations” test condition. The T
IA
/E
IA
specification load is for reference only.
NOTE 2: The scope inputs are assumed to have a 2pF load to ground. T
IA
/E
IA
– 644 specifies 5pF between the output pair.
With C
L
= 8pF, this gives the test circuit appropriate 5pF equivalent load.
Symbol V
DD
= 2.5V ± 0.2V Unit
C
L
0
(1)
pF
8
(1,2)
pF
R
L
50
VDD
D.U.T.
A
A
Qn
Qn
Pulse
Generator
RL
RL
VOS VOD
VDD/2
D.U.T.
A
A
Qn
Qn
Pulse
Generator
50Ω
50Ω
Z = 50Ω
Z = 50Ω
SCOPE
C
L
-VDD/2
CL
P1-P3P4-P6P7-P9P10-P12P13-P15P16-P16

5T9304PGG

Mfr. #:
Buy 5T9304PGG
Manufacturer:
IDT
Description:
Clock Buffer 450 MHz 2.5V LVDS 1:4 Clock Buffer
Lifecycle:
New from this manufacturer.
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