9
FN9177.3
June 25, 2009
improved with a reduction of unnecessary switching losses
by reducing the PWM frequency. It is characteristic of the R
3
architecture for the PWM frequency to decrease while in
diode emulation. The extent of the frequency reduction is
proportional to the reduction of load current. The ISL6269
features an audio filter that clamps the minimum PWM
frequency to a level beyond human hearing when the output
load current becomes low enough.
With FCCM pulled low, the converter will automatically enter
DEM after the PHASE pin has detected positive voltage,
while the LG gate-driver pin is high, for eight consecutive
PWM pulses. The converter will return to CCM on the
following cycle after the PHASE pin detects negative
voltage, indicating that the body diode of the low-side
MOSFET is conducting positive inductor current.
Overcurrent and Short-Circuit Protection
The overcurrent protection (OCP) and short circuit protection
(SCP) setpoint is programmed with resistor R
SEN
that is
connected across the ISEN and PHASE pins. The PHASE pin
is connected to the drain terminal of the low-side MOSFET.
The SCP setpoint is internally set to twice the OCP setpoint.
When an OCP or SCP fault is detected, the PGOOD pin will
pulldown to
30and latch off the converter. The fault will
remain latched until the EN pin has been pulled below the
falling EN threshold voltage V
ENTHF
or if V
VCC
has decayed
below the falling POR threshold voltage
V
VCC_THF
.
The OCP circuit does not directly detect the DC load current
leaving the converter. The OCP circuit detects the peak of
positive-flowing output inductor current. The low-side
MOSFET drain current I
D
is assumed to be equal to the
positive output inductor current when the high-side MOSFET
is off. The inductor current develops a negative voltage
across the r
DS(ON)
of the low-side MOSFET that is
measured shortly after the LG gate-driver output goes high.
The ISEN pin sources the OCP sense current I
SEN,
through
the OCP programming resistor R
SEN,
forcing the ISEN pin to
zero volts with respect to the GND pin. The negative voltage
across the PHASE and GND pins is nulled by the voltage
dropped across R
SEN
as I
SEN
conducts through it. An OCP
fault occurs if I
SEN
rises above the OCP threshold current
I
OC
while attempting to null the negative voltage across the
PHASE and GND pins. I
SEN
must exceed I
OC
on all the
PWM pulses that occur within 20µs. If I
SEN
falls below I
OC
on a PWM pulse before 20µs has elapsed, the timer will be
reset. An SCP fault will occur within 10µs when I
SEN
exceeds twice I
OC.
The relationship between I
D
and I
SEN
is
written as:
The value of R
SEN
is then written as:
Where:
-R
SEN
() is the resistor used to program the
overcurrent setpoint
-I
SEN
is the current sense current that is sourced from
the ISEN pin
-I
OC
is the I
SEN
threshold current sourced from the ISEN
pin that will activate the OCP circuit
-I
FL
is the maximum continuous DC load current
-I
PP
is the inductor peak-to-peak ripple current
-OC
SP
is the desired overcurrent setpoint expressed as
a multiplier relative to I
FL
Overvoltage Protection
When an OVP fault is detected, the PGOOD pin will
pull-down to 60
and latch-off the converter. The OVP fault
will remain latched until the V
VCC
has decayed below the
falling POR threshold voltage
V
VCC_THF
.
The OVP fault detection circuit triggers after the voltage
across the FB and GND pins has increased above the rising
overvoltage threshold V
OVR.
Although the converter has
latched-off in response to an OVP fault, the LG gate-driver
output will retain the ability to toggle the low-side MOSFET
on and off, in response to the output voltage transversing the
V
OVR
and V
OVF
thresholds.
Undervoltage Protection
When a UVP fault is detected, the PGOOD pin will pull down
to 95
and latch-off the converter. The fault will remain
latched until the EN pin has been pulled below the falling EN
threshold voltage V
ENTHF
or if V
VCC
has decayed below the
falling POR threshold voltage
V
VCC_THF
.
The UVP fault
detection circuit triggers after the voltage across the FB and
GND pins has fallen below the undervoltage threshold V
UV
.
Over-Temperature
When the temperature of the ISL6269 increases above the
rising threshold temperature T
OTR
, the IC will enter an OTP
state that suspends the PWM , forcing the LG and UG
gate-driver outputs low. The status of the PGOOD pin does
not change nor does the converter latch-off. The PWM
remains suspended until the IC temperature falls below the
hysteresis temperature T
OTHYS
at which time normal PWM
operation resumes. The OTP state can be reset if the EN pin
is pulled below the falling EN threshold voltage V
ENTHF
or if
V
VCC
decays below the falling POR threshold voltage
V
VCC_THF
. All other protection circuits function normally
during OTP. It is likely that the IC will detect an UVP fault
because in the absence of PWM, the output voltage
immediately decays below the undervoltage threshold V
UV
;
the PGOOD pin will pull-down to 95and latch-off the
converter. The UVP fault will remain latched until the EN pin
has been pulled below the falling EN threshold voltage
V
ENTHF
or if V
VCC
has decayed below the falling POR
threshold voltage
V
VCC_THF
.
I
SEN
R
SEN
I
D
r
DS ON
=
(EQ. 3)
(EQ. 4)
R
SEN
I
FL
I
PP
2
---------
+
OC
SP
r
DS ON
I
OC
----------------------------------------------------------------------------
=
ISL6269
