MP6905- FAST TURN-OFF, INTELLIGENT RECTIFIER
MP6905 Rev. 1.0 www.MonolithicPower.com 13
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LAYOUT GUIDELINES
Sensing for V
D
/V
SS
The sensing connection (V
D
/V
SS
) should be
closed off to the MOSFET (drain/source). Make
the sensing loop as small as possible and place
the VD resistor close to the VD. Keep the IC out
of the power loop to make sure the sensing
loop and power loop won’t interrupt each other
(see Figure 11).
Figure 11:Voltage Sensing for V
D
/V
SS
on MP6905
Sensing for V
D
/V
SS
A decoupling ceramic capacitor (no smaller than
1uF) from V
DD
to PGND should be close to the IC
for adequate filtering.
Gate-Driver Loop
To minimize the parasitic inductance, the gate-
driver loop should be as small as possible. Keep
the driver signal far away from the VD sensing
trace on the layout.
Figure 12: TO220 Package SR FET
Figure12 shows a layout example of a single
layer with a through-hole transformer and TO220
package SR FET (see the application circuit on
page 1). R
SN
and C
SN
provide the RC snubber
network for the SR FET.
The sensing loop (V
D
/V
SS
to the SR FET) is
minimized and separates from the power loop.
The V
DD
decoupling capacitor (C4) is placed
beside the V
DD
.
Figure 13 shows a layout example of a single
layer with a PowerPAK/SO8 package SR FET,
which also has a minimized sensing loop and
power loop that won’t interrupt each other.
0
Q1
R3
R2
D2
C5
R5
R4
C3
C4
LAYOUT TRACE
COMPONENTS PAD
JUMP WIRE
Figure 13: PowerPAK/SO8 Package SR FET
