12
LTC1286/LTC1298
Start Bit
The first “logical one” clocked into the D
IN
input after CS
goes low is the start bit. The start bit initiates the data
transfer. The LTC1298 will ignore all leading zeros which
precede this logical one. After the start bit is received, the
remaining bits of the input word will be clocked in. Further
inputs on the D
IN
pin are then ignored until the next CS
cycle.
Multiplexer (MUX) Address
The bits of the input word following the START bit assign
the MUX configuration for the requested conversion. For
a given channel selection, the converter will measure the
voltage between the two channels indicated by the + and
– signs in the selected row of the following tables. In
single-ended mode, all input channels are measured with
respect to GND.
APPLICATION INFORMATION
WUU
U
Input Data Word
The LTC1286 requires no D
IN
word. It is permanently
configured to have a single differential input. The conver-
sion result appears on the D
OUT
line. The data format is
MSB first followed by the LSB sequence. This provides
easy interface to MSB or LSB first serial ports. For MSB
first data the CS signal can be taken high after B0 (see
Figure 1). The LTC1298 clocks data into the D
IN
input on
the rising edge of the clock. The input data words are
defined as follows:
MSBF bit is a logical zero, LSB first data will follow the
normal MSB first data on the D
OUT
line. (see Operating
Sequence)
Transfer Curve
The LTC1286/LTC1298 are permanently configured for
unipolar only. The input span and code assignment for
this conversion type are shown in the following figures.
MSB First/LSB First (MSBF)
The output data of the LTC1298 is programmed for
MSB first or LSB first sequence using the MSBF bit.
When the MSBF bit is a logical one, data will appear on
the D
OUT
line in MSB first format. Logical zeros will be
filled in indefinitely following the last data bit. When the
Operation with D
IN
and D
OUT
Tied Together
The LTC1298 can be operated with D
IN
and D
OUT
tied
together. This eliminates one of the lines required to
communicate to the microprocessor (MPU). Data is trans-
mitted in both directions on a single wire. The processor
pin connected to this data line should be configurable as
either an input or an output. The LTC1298 will take control
of the data line and drive it low on the 4th falling CLK edge
after the start bit is received (see Figure 3). Therefore the
processor port line must be switched to an input before
this happens to avoid a conflict.
In the Typical Applications section, there is an example of
interfacing the LTC1298 with D
IN
and D
OUT
tied together to
the Intel 8051 MPU.
OUTPUT CODE
•
•
•
1 1 1 1 1 1 1 1 1 1 1 1 1 1
1 1 1 1 1 1 1 1 1 1 1 1 1 0
0 0 0 0 0 0 0 0 0 0 0 0 0 1
0 0 0 0 0 0 0 0 0 0 0 0 0 0
INPUT VOLTAGE
V
REF
– 1LSB
V
REF
– 2LSB
•
•
•
1LSB
0V
INPUT VOLTAGE
(V
REF
= 5.000V)
4.99878V
4.99756V
•
•
•
0.00122V
0V
LTC1286/98 • AI05
Transfer Curve
0V
1LSB
V
REF
–2LSB
V
REF
4096
V
REF
–1LSB
V
REF
V
IN
0 0 0 0 0 0 0 0 0 0 0 1
0 0 0 0 0 0 0 0 0 0 0 0
1 1 1 1 1 1 1 1 1 1 1 1
1 1 1 1 1 1 1 1 1 1 1 0
•
•
•
LTC1286/98 • AI04
1LSB =
MUX ADDRESS
SGL/DIFF
1
1
0
0
ODD/SIGN
0
1
0
1
CHANNEL #
0
+
+
–
1
+
–
+
GND
–
–
SINGLE-ENDED
MUX MODE
DIFFERENTIAL
MUX MODE
LTC1096/8 • AI03
SGL/
DIFF
ODD/
SIGN
MSBFSTART
MUX
ADDRESS
MSB FIRST/
LSB FIRST
LTC1096/9 • AI02
LTC1298 Channel Selection
Output Code
