13
LTC1286/LTC1298
APPLICATION INFORMATION
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SAMPLE RATE (kHz)
0.1k
1
10
100
1000
1k 10k 100k
LT1286/98 G03
SUPPLY CURRENT (µA)
T
A
= 25°C
V
CC
= V
REF
= 5V
f
CLK
= 200kHz
LTC1286
LTC1298
input becomes high impedance at the end of each conver-
sion leaving the CLK running to clock out the LSB first data
or zeroes (see Figures 1 and 2). If the CS is not running rail-
to-rail, the input logic buffer will draw current. This current
may be large compared to the typical supply current. To
obtain the lowest supply current, bring the CS pin to
ground when it is low and to supply voltage when it is high.
When the CS pin is high (= supply voltage), the converter
is in shutdown mode and draws only leakage current. The
status of the D
IN
and CLK input have no effect on supply
current during this time. There is no need to stop D
IN
and
CLK with CS = high; they can continue to run without
drawing current.
Minimize CS Low Time
In systems that have significant time between conver-
sions, lowest power drain will occur with the minimum CS
low time. Bringing CS low, transferring data as quickly as
possible, and then bringing it back high will result in the
lowest current drain. This minimizes the amount of time
the device draws power. After a conversion the ADC
automatically shuts down even if CS is held low (see
Figures 1 and 2). If the clock is left running to clock out
LSB-data or zero, the logic will draw a small current.
Figure 5 shows that the typical supply current with CS =
ground varies from 1µA at 1kHz to 35µA at 200kHz. When
CS = V
CC
, the logic is gated off and no supply current is
drawn regardless of the clock frequency.
Shutdown
The LTC1286/LTC1298 are equipped with automatic shut-
down features. They draw power when the CS pin is low
and shut down completely when that pin is high. The bias
circuit and comparator powers down and the reference
ACHIEVING MICROPOWER PERFORMANCE
With typical operating currents of 250µA and automatic
shutdown between conversions, the LTC1286/LTC1298
achieves extremely low power consumption over a wide
range of sample rates (see Figure 4). The auto-shutdown
allows the supply curve to drop with reduced sample rate.
Several things must be taken into account to achieve such
a low power consumption.
Figure 4. Automatic Power Shutdown Between Conversions
Allows Power Consumption to Drop with Sample Rate.
1
2 3 4
CS
CLK
DATA (D
IN
/D
OUT
)
START SGL/DIFF ODD/SIGN MSBF B11 B10
•••
MSBF BIT LATCHED
BY LTC1298
LTC1298 CONTROLS DATA LINE AND SENDS
A/D RESULT BACK TO MPU
MPU CONTROLS DATA LINE AND SENDS
MUX ADDRESS TO LTC1298
PROCESSOR MUST RELEASE
DATA LINE AFTER 4TH RISING CLK
AND BEFORE THE 4TH FALLING CLK
LTC1298 TAKES CONTROL OF DATA LINE
ON 4TH FALLING CLK
LTC1286/98 F03
Figure 3. LTC1298 Operation with D
IN
and D
OUT
Tied Together
14
LTC1286/LTC1298
Figure 5. Shutdown current with CS high is 1nA typically,
regardless of the clock. Shutdown current with CS = ground
varies from 1µA at 1kHz to 35µA at 200kHz.
APPLICATION INFORMATION
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Clock Frequency
The maximum recommended clock frequency is 200kHz
for the LTC1286/LTC1298 running off a 5V supply. With
the supply voltage changing, the maximum clock fre-
quency for the devices also changes (see the typical curve
of Maximum Clock Rate vs Supply Voltage). If the maxi-
mum clock frequency is used, care must be taken to
ensure that the device converts correctly.
Mixed Supplies
It is possible to have a microprocessor running off a 5V
supply and communicate with the LTC1286 operating on
a 9V supply. The requirement to achieve this is that the
outputs of CS and CLK from the MPU have to be able to trip
the equivalent inputs of the LTC1286 and the output of
D
OUT
from the LTC1286 must be able to toggle the
equivalent input of the MPU (see typical curve of Digital
Input Logic Threshold vs Supply Voltage). With the
LTC1286 operating on a 9V supply, the output of D
OUT
may
go between 0V and 9V. The 9V output may damage the
MPU running off a 5V supply. The way to get around this
possibility is to have a resistor divider on D
OUT
(Figure 6)
and connect the center point to the MPU input. It should
be noted that to get full shutdown, the CS input of the
LTC1286 must be driven to the V
CC
voltage to keep the CS
input buffer from drawing current. An alternative is to
leave CS low after a conversion, clock data until D
OUT
outputs zeros, and then stop the clock low.
D
OUT
Loading
Capacitive loading on the digital output can increase power
consumption. A 100pF capacitor on the D
OUT
pin can add
more than 50µA to the supply current at a 200kHz clock
frequency. An extra 50µA or so of current goes into
charging and discharging the load capacitor. The same
goes for digital lines driven at a high frequency by any logic.
The C × V × f currents must be evaluated and the trouble-
some ones minimized.
OPERATING ON OTHER THAN 5V SUPPLIES (LTC1286)
The LTC1286 operates from 4.5V to 9V supplies and the
LTC1298 operates from a 5V supply. To operate the LTC1286
on other than 5V supplies a few things must be kept in
mind.
Input Logic Levels
The input logic levels of CS, CLK and D
IN
are made to meet
TTL on a 5V supply. When the supply voltage varies, the
input logic levels also change. For the LTC1286 to sample
and convert correctly, the digital inputs have to be in the
proper logical low and high levels relative to the operating
supply voltage (see typical curve of Digital Input Logic
Threshold vs Supply Voltage). If achieving micropower
consumption is desirable, the digital inputs must go rail-to-
rail between supply voltage and ground (see ACHIEVING
MICROPOWER PERFORMANCE section).
FREQUENCY (kHz)
1
0.002
SUPPLY CURRENT (µA)
5
1
0
15
20
25
35
20
100
140
LT1286/98 G01
10
30
80
180
200
40
60
120 160
CS = 0
(AFTER CONVERSION)
T
A
= 25°C
V
CC
= V
REF
= 5V
CS = V
CC
+IN
–IN
GND
V
CC
CLK
D
OUT
V
REF
50k
50k
5V
4.7µF
MPU
(e.g. 8051)
5V
P1.4
P1.3
P1.2
LTC1286/98 • F06
DIFFERENTIAL INPUTS
COMMON-MODE RANGE
0V TO 5V
9V
LTC1286
CS
Figure 6. Interfacing a 9V Powered LTC1286 to a 5V System
15
LTC1286/LTC1298
APPLICATION INFORMATION
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BOARD LAYOUT CONSIDERATIONS
Grounding and Bypassing
The LTC1286/LTC1298 are easy to use if some care is
taken. They should be used with an analog ground plane
and single point grounding techniques. The GND pin
should be tied directly to the ground plane.
The V
CC
pin should be bypassed to the ground plane with
a 10µF tantalum capacitor with leads as short as possible.
If the power supply is clean, the LTC1286/LTC1298 can
also operate with smaller 1µF or less surface mount or
ceramic bypass capacitors. All analog inputs should be
referenced directly to the single point ground. Digital
inputs and outputs should be shielded from and/or routed
away from the reference and analog circuitry.
SAMPLE-AND-HOLD
Both the LTC1286 and the LTC1298 provide a built-in
sample-and-hold (S&H) function to acquire signals. The
S&H of the LTC1286 acquires input signals from “+” input
relative to “–” input during the t
SMPL
time (see Figure 1).
However, the S&H of the LTC1298 can sample input
signals in the single-ended mode or in the differential
inputs during the t
SMPL
time (see Figure 7).
Single-Ended Inputs
The sample-and-hold of the LTC1298 allows conversion
of rapidly varying signals. The input voltage is sampled
during the t
SMPL
time as shown in Figure 7. The sampling
interval begins as the bit preceding the MSBF bit is shifted
in and continues until the falling CLK edge after the MSBF
bit is received. On this falling edge, the S&H goes into hold
mode and the conversion begins.
Figure 7. LTC1298 “+” and “–” Input Settling Windows
CLK
D
IN
D
OUT
"+" INPUT
"–" INPUT
SAMPLE HOLD
"+" INPUT MUST
SETTLE DURING
THIS TIME
t
SMPL
t
CONV
CS
SGL/DIFFSTART MSBF DON'T CARE
1ST BIT TEST "–" INPUT MUST
SETTLE DURING THIS TIME
B11
LTC1096/8 • F07

LTC1286IS8#PBF

Mfr. #:
Manufacturer:
Analog Devices Inc.
Description:
Analog to Digital Converters - ADC uP Smpl 12-B A/D Convs In S0-8 Packages
Lifecycle:
New from this manufacturer.
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