Nexperia
74AUP1T97
Low-power configurable gate with voltage-level translator
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Date of release: 28 March 2017
Document identifier: 74AUP1T97
Contents
1 General description ............................................ 1
2 Features and benefits .........................................1
3 Ordering information .......................................... 2
4 Marking .................................................................2
5 Pinning information ............................................ 3
5.1 Pinning ............................................................... 3
5.2 Pin description ................................................... 4
6 Functional description ........................................4
7 Functional diagram .............................................4
8 Logic configurations ...........................................5
9 Limiting values ....................................................6
10 Recommended operating conditions ................ 6
11 Static characteristics .......................................... 7
12 Dynamic characteristics ................................... 10
12.1 Waveforms and test circuit .............................. 11
13 Package outline .................................................13
14 Abbreviations .................................................... 20
15 Revision history ................................................ 20
16 Legal information ..............................................21