REV. 0
ADM1022
–12–
FAULT TOLERANT FAN CONTROL
The ADM1022 incorporates a fault tolerant fan control capabil-
ity that is tied to operation of the THERM output. It can over-
ride the setting of the analog output and force it to maximum to
give full fan speed in the event of a critical over-temperature
problem, even if, for some reason, this has not been handled by
the system software.
There are four temperature set point registers that will activate
the fault tolerant fan control. Two of these limits are program-
mable by the user and two are hardware (read-only) registers
that will operate if the user does not program any limits. The
fault tolerant fan control is activated if a limit is exceeded for
three or more consecutive readings. These limits are separate
from the normal high and low temperature limits for the INT
output, which do not affect the fault tolerant fan control or
THERM output.
A hardware limit of 70°C for the on-chip temperature sensor is
programmed into the register at address 13h. For the remote
sensors, a hardware limit of 100°C is programmed in to the
register at address 17h. These are the default limits and the ana-
log output will be forced to full-scale if the on-chip sensor reads
more than 70°C or either of the remote sensors reads more than
100°C. This makes the fault tolerant fan control fail-safe in that it
will operate at these temperatures even if the user has programmed
no other limits, or in the event of a software malfunction.
The user may override these default limits by programming new
limits into registers at address 14h for the on-chip sensor and
18h for the remote sensors. The default values in these registers
are the same as for the read-only registers (70°C and 100°C),
but they may be programmed with higher or lower values.
Once registers 13h and 14h have been programmed, or if the
default is acceptable, Bit 1 of the configuration register must be
set to “1.” This bit is a write-once bit that can only be written to
“1” and it has two effects:
1. It makes the values in registers 13h and 14h the active limits,
and disables read-only registers 17h and 18h.
2. It locks the data into registers 13h and 14h, so they cannot
be changed until the lock bit is reset, which is when RST2 is
asserted or a Power-On Reset occurs.
Once the hardware override of the analog output is triggered, it
will only return to normal operation after three consecutive
measurements that are five degrees lower than each of the above
limits.
The analog output can also be forced to full-scale by pulling the
THERM pin (Pin 11) low. Bit 6 of the Status Register is also set.
Whenever FAN_SPD output is forced to full-scale, the FAN_OFF
output is negated.
THE ADM1022 INTERRUPT SYSTEM
The ADM1022 has two interrupt outputs, INT and THERM.
These have different functions. INT responds to violations of
software programmed temperature limits and its interrupt sources
are maskable, as described in more detail later. THERM is
intended as a “fail-safe” interrupt output that cannot be masked.
Interrupts and status bits are only set if a limit is exceeded for at
least three consecutive conversions.
Operation of the INT output is illustrated in Figure 15. Assum-
ing that the temperature starts off within the programmed limits
and that temperature interrupt sources are not masked, INT
will go low if the temperature measured by any of the internal or
external sensors goes outside the programmed high or low
temperature limit for that sensor. INT also goes low whenever
THERM is low.
100ⴗC
90ⴗC
80ⴗC
70ⴗC
60ⴗC
50ⴗC
40ⴗC
TEMP
HIGH LIMIT
LOW LIMIT
ACPI CONTROL
METHODS
CLEAR EVENT
INT
*
*
*
*
*
*
*ACPI AND DEFAULT CONTROL METHODS
ADJUST TEMPERATURE LIMIT VALUES
Figure 15. Operation of
INT
Output
Once the interrupt has been cleared, it will not be reasserted
even if the temperature remains outside the limit previously
exceeded. However, INT will be reasserted if:
a) the temperature goes outside the other limit for the sensor
or
b) the previously exceeded limit is reprogrammed and the tem-
perature is then outside the new limit on the next conversion
cycle
or
c) an interrupt is generated by another source.
INTERRUPT MASKING
Any of the bits in the Interrupt Status Register can be masked
out by setting the corresponding mask bit in the Interrupt Mask
Register. That interrupt source will then no longer generate an
interrupt. However, the bits in the status register will be set as
normal.
INTERRUPT CLEARING
Reading the Interrupt Status Register will output the contents of
the Register, then clear it. It will remain cleared until the moni-
toring cycle updates it, so the next read operation should not be
performed on the register until this has happened, or the result
will be invalid.
The INT output is cleared with the INT_Clear bit, which is Bit
2 of the Configuration Register, without affecting the contents
of the Interrupt (INT) Status Registers.
INTERRUPT STATUS MIRROR REGISTER
Whenever a bit in the Interrupt Status Register is set, the corre-
sponding bit is also set in the mirror register at address 4Ch.
This register allows a second management system to access the
status data without worrying about clearing the data. The data
in this register is for reading only and has no effect on the inter-
rupt output. The contents of this register are cleared when read.
