M41T80 Clock operation
Doc ID 9074 Rev 5 17/27
3.5 Output driver pin
When the AFE bit and SQWE bit are not set, the IRQ/OUT/SQW pin becomes an output
driver that reflects the contents of D7 of the control register. In other words, when D7 (OUT
bit) of address location 08h is a '0,' then the IRQ
/OUT/SQW pin will be driven low.
Note: The IRQ
/OUT/SQW pin is an open drain which requires an external pull-up resistor.
3.6 Preferred power-on default
When powering the device up from ground (0 V), the following register bits are set to a '0'
state: ST; AFE; and SQWE. The following bits are set to a '1' state: OUT and 32KE (see
Table 6: Preferred power-on default values on page 17).
Table 6. Preferred power-on default values
Condition ST OUT AFE SQWE 32KE
Power-up
(1)
1. If V
CC
falls to a voltage, 0 V < V
CC
< 2.0 V, these bits should be rewritten by the user.
0100 1