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J112RL1

P1-P3P4-P5
© Semiconductor Components Industries, LLC, 2006
March, 2006 − Rev. 2
1 Publication Order Number:
J111/D
J111, J112
JFET Chopper Transistors
N−Channel — Depletion
Features
• Pb−Free Packages are Available*
MAXIMUM RATINGS
Rating Symbol Value Unit
Drain−Gate Voltage V
DG
−35 Vdc
Gate−Source Voltage V
GS
−35 Vdc
Gate Current I
G
50 mAdc
Total Device Dissipation @ T
A
= 25°C
Derate above = 25°C
P
D
350
2.8
mW
mW/°C
Lead Temperature T
L
300 °C
Operating and Storage Junction
Temperature Range
T
J
, T
stg
−65 to +150 °C
Maximum ratings are those values beyond which device damage can occur.
Maximum ratings applied to the device are individual stress limit values (not
normal operating conditions) and are not valid simultaneously. If these limits are
exceeded, device functional operation is not implied, damage may occur and
reliability may be affected.
*For additional information on our Pb−Free strategy and soldering details, please
download the ON Semiconductor Soldering and Mounting Techniques
Reference Manual, SOLDERRM/D.
MARKING DIAGRAM
http://onsemi.com
TO−92
CASE 29−11
STYLE 5
1
2
3
J11x
AYWW G
G
1 DRAIN
2 SOURCE
3
GATE
See detailed ordering and shipping information in the package
dimensions section on page 2 of this data sheet.
ORDERING INFORMATION
J11x = Device Code
x = 1 or 2
A = Assembly Location
Y = Year
WW = Work Week
G = Pb−Free Package
(Note: Microdot may be in either location)
J111, J112
http://onsemi.com
2
ELECTRICAL CHARACTERISTICS (T
A
= 25°C unless otherwise noted)
Characteristic
Symbol Min Max Unit
OFF CHARACTERISTICS
Gate−Source Breakdown Voltage
(I
G
= −1.0 mAdc)
V
(BR)GSS
35 − Vdc
Gate Reverse Current
(V
GS
= −15 Vdc)
I
GSS
− −1.0 nAdc
Gate Source Cutoff Voltage
(V
DS
= 5.0 Vdc, I
D
= 1.0 mAdc) J111
J112
V
GS(off)
−3.0
−1.0
−10
−5.0
Vdc
Drain−Cutoff Current
(V
DS
= 5.0 Vdc, V
GS
= −10 Vdc)
I
D(off)
− 1.0 nAdc
ON CHARACTERISTICS
Zero−Gate−Voltage Drain Current
(1)
(V
DS
= 15 Vdc) J111
J112
I
DSS
20
5.0
2.0
−
−
−
mAdc
Static Drain−Source On Resistance
(V
DS
= 0.1 Vdc) J111
J112
r
DS(on)
−
−
30
50
W
Drain Gate and Source Gate On−Capacitance
(V
DS
= V
GS
= 0, f = 1.0 MHz)
C
dg(on)
+
C
sg(on)
− 28 pF
Drain Gate Off−Capacitance
(V
GS
= −10 Vdc, f = 1.0 MHz)
C
dg(off)
− 5.0 pF
Source Gate Off−Capacitance
(V
GS
= −10 Vdc, f = 1.0 MHz)
C
sg(off)
− 5.0 pF
1. Pulse Width = 300 ms, Duty Cycle = 3.0%.
ORDERING INFORMATION
Device Package Shipping
†
J111RL1 TO−92
2000 Units / Tape & Reel
J111RL1G TO−92
(Pb−Free)
J111RLRA TO−92
2000 Units / Tape & Reel
J111RLRAG TO−92
(Pb−Free)
J111RLRP TO−92
2000 Units / Tape & Reel
J111RLRPG TO−92
(Pb−Free)
J112 TO−92
1000 Units / Bulk
J112G TO−92
(Pb−Free)
J112RL1 TO−92
2000 Units / Tape & Reel
J112RL1G TO−92
(Pb−Free)
J112RLRA TO−92
2000 Units / Tape & Reel
J112RLRAG TO−92
(Pb−Free)
†For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging
Specifications Brochure, BRD8011/D.
J111, J112
http://onsemi.com
3
t
f
, FALL TIME (ns) t
r
, RISE TIME (ns)
t
d(on)
, TURN−ON DELAY TIME (ns)
1000
1.0
2.0
5.0
10
20
50
100
200
500
0.5 0.7 1.0 2.0 3.0 5.0 7.0 10 20 30 50
I
D
, DRAIN CURRENT (mA)
Figure 1. Turn−On Delay Time
R
K
= 0
T
J
= 25°C
J111
J112
J113
V
GS(off)
= 12 V
= 7.0 V
= 5.0 V
R
K
= R
D
′
1000
1.0
2.0
5.0
10
20
50
100
200
500
0.5 0.7 1.0 2.0 3.0 5.0 7.0 10 20 30 50
I
D
, DRAIN CURRENT (mA)
Figure 2. Rise Time
R
K
= R
D
′
R
K
= 0
T
J
= 25°C
J111
J112
J113
V
GS(off)
= 12 V
= 7.0 V
= 5.0 V
1000
1.0
2.0
5.0
10
20
50
100
200
500
0.5 0.7 1.0 2.0 3.0 5.0 7.0 10 20 30 50
I
D
, DRAIN CURRENT (mA)
Figure 3. Turn−Off Delay Time
R
K
= R
D
′
R
K
= 0
T
J
= 25°C
J111
J112
J113
V
GS(off)
= 12 V
= 7.0 V
= 5.0 V
t
d(off)
, TURN−OFF DELAY TIME (ns)
1000
1.0
2.0
5.0
10
20
50
100
200
500
0.5 0.7 1.0 2.0 3.0 5.0 7.0 10 20 30 50
I
D
, DRAIN CURRENT (mA)
Figure 4. Fall Time
R
K
= R
D
′
R
K
= 0
T
J
= 25°C
J111
J112
J113
V
GS(off)
= 12 V
= 7.0 V
= 5.0 V
TYPICAL SWITCHING CHARACTERISTICS
NOTE 1
The switching characteristics shown above were measured using a te
st
circuit similar to Figure 5. At the beginning of the switching interva
l,
the gate voltage is at Gate Supply Voltage (−V
GG
). The Drain−Sourc
e
Voltage (V
DS
) is slightly lower than Drain Supply Voltage (V
DD
) du
e
to the voltage divider. Thus Reverse Transfer Capacitance (C
rss
) o
r
Gate−Drain Capacitance (C
gd
) is charged to V
GG
+ V
DS
.
During the turn−on interval, Gate−Source Capacitance (C
gs
)
discharges through the series combination of R
Gen
and R
K
. C
gd
mu
st
discharge to V
DS(on)
through R
G
and R
K
in series with the paralle
l
combination of effective load impedance (R′
D
) and Drain−Sourc
e
Resistance (r
ds
). During the turn−off, this charge flow is reversed.
Predicting turn−on time is somewhat difficult as the channel resistanc
e
r
ds
is a function of the gate−source voltage. While C
gs
discharges, V
G
S
approaches zero and r
ds
decreases. Since C
gd
discharges through r
ds
,
turn−on time is non−linear. During turn−off, the situation is reverse
d
with r
ds
increasing as C
gd
charges.
The above switching curves show two impedance conditions; 1) R
K
is equal to R
D
, which simulates the switching behavior of cascade
d
stages where the driving source impedance is normally the loa
d
impedance of the previous stage, and 2) R
K
= 0 (low impedance) th
e
driving source impedance is that of the generator.
R
GEN
50 W
V
GEN
INPUT
R
K
50 W
R
GG
V
GG
50 W
OUTPUT
R
D
+V
DD
R
T
SET V
DS(off)
= 10 V
INPUT PULSE
t
r
t
f
PULSE WIDTH
DUTY CYCLE
≤ 0.25 ns
≤ 0.5 ns
= 2.0 ms
≤ 2.0%
R
GG
& R
K
R
D
Ȁ+
R
D
(R
T
) 50)
R
D
) R
T
) 50
Figure 5. Switching Time Test Circuit
P1-P3P4-P5

J112RL1

Mfr. #:
Buy J112RL1
Manufacturer:
ON Semiconductor
Description:
JFET 35V 10mA
Lifecycle:
New from this manufacturer.
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