MT90863 Data Sheet
30
Zarlink Semiconductor Inc.
Bit Name Description
15 - 0 RD15 - RD0 Read Data Bits. Data transferred from one of the internal memory locations.
Table 15 - Data Read (DRR) Register Bits
Bit Name Description
15,14 Unused Must be zero for normal operation.
13 BV
/C Variable /Constant Throughput Delay. This bit is used to select either
variable (low) or constant delay (high) modes on a per-channel basis for the
local interface streams.
12 BMC Message Channel. When 1, the backplane connection memory contents are
output on the corresponding output channel and stream. Only the lower byte
(bit 7 - bit 0) will be output to the backplane interface STio pins. When 0, the
local data memory address of the switched STi input channel and stream is
loaded into the backplane connection memory.
11 DC Directional Control. This bit enables the STio pindrivers on a per-channel
basis. When 1, the STio output driver functions normally. When 0, the STio
output driver is in a high-impedance state.
10-7
(Note 1)
BSAB3-0 Source Stream Address Bits. The binary value is the number of the data
stream for the source of the connection.
6-0
(Note 1)
BCAB6-0 Source Channel Address Bits. The binary value identifies the channel for
the connection source.
Note 1: If bit 12 (BMC) of the corresponding backplane connection memory location is 1 (device in message mode), then these
entire 8 bits (BSAB0, BCAB6 - BCAB0) are output on the output channel and stream associated with this location.
Table 16 - Blackplane Connection Memory Bits
Read Address: 0E
H
for DRR register,
Reset value: 0000
H
765432108910111213
RD0RD1RD2
RD3
1415
RD4RD5RD6RD7RD8RD9RD10RD11RD12RD13RD14RD15
765432108910111213
BCABBCABBCABBSAB
BCABBCABBCABBSABBSABBSAB
DCBMC
14
0
15
BV/C0
32106543210
BCAB
