2©2017 Integrated Device Technology, Inc. September 22, 2017
8S89834I Datasheet
Table 1. Pin Descriptions
NOTE: Pullup refers to internal input resistors. See Table 2, Pin Characteristics, for typical values.
Table 2. Pin Characteristics
Number Name Type Description
1, 2 Q1, nQ1 Output Differential output pair. LVPECL/ECL interface levels.
3, 4 Q2, nQ2 Output Differential output pair. LVPECL/ECL interface levels.
5, 6 Q3, nQ3 Output Differential output pair. LVPECL/ECL interface levels.
7, 14 V
cc
Power Positive supply pins.
8 EN Input Pullup
Synchronizing clock enable. When LOW, Q outputs will go LOW and nQ outputs will
go HIGH on the next LOW transition at IN inputs. Input threshold is V
CC
/2V. Includes a
37k
pullup resistor. Default state is HIGH when left floating. The internal latch is
clocked on the falling edge of the input signal IN1, IN2.
LVTTL/LVCMOS interface levels.
9 IN2 Input Pullup Single-ended clock input. LVCMOS/LVTTL interface levels.
10 nc Unused No connect.
11 SEL Input Pullup
Select clock input. When LOW, selects IN2 and when HIGH selects IN1.
LVCMOS/LVTTL interface levels.
12 IN1 Input Pullup Single-ended clock input. LVCMOS/LVTTL interface levels.
13 V
EE
Power Negative supply pin.
15, 16 Q0, nQ0 Output Differential output pair. LVPECL/ECL interface levels.
Symbol Parameter Test Conditions Minimum Typical Maximum Units
R
PULLUP
Input Pullup Resistor 37 k
