7©2017 Integrated Device Technology, Inc. September 22, 2017
8S89834I Datasheet
Parameter Measurement Information
3.3V LVPECL Output Load AC Test Circuit
Part-to-Part Skew
Setup & Hold Time
2.5V LVPECL Output Load AC Test Circuit
Output Skew
Propagation Delay
SCOPE
Qx
nQx
V
EE
V
CC
2V
-1.3V±0.33V
nQx
Qx
nQy
Qy
tsk(pp)
P
art 1
P
art 2
t
HOLD
t
SET-UP
V
DD
2
IN1, IN2
EN
V
CC
2V
-0.5V ± 0.125V
Qx
nQx
Qy
nQy
tp
LH
tp
HL
nQ0:nQ3
Q0:Q3
IN1, IN2
8©2017 Integrated Device Technology, Inc. September 22, 2017
8S89834I Datasheet
Parameter Measurement Information, continued
Output Rise/Fall Time
Differential Output Voltage Swing
Switch Over
Output Duty Cycle/Pulse Width/Period
Application Information
Recommendations for Unused Input and Output Pins
Inputs:
IN Inputs
For applications not requiring the use of a clock input, it can be left
floating. Though not required, but for additional protection, a 1k
resistor can be tied from the IN input to ground.
LVCMOS Control Pins
All control pins have internal pullups; additional resistance is not
required but can be added for additional protection. A 1k resistor
can be used.
Outputs:
LVPECL Outputs
All unused LVPECL outputs can be left floating. We recommend that
there is no trace attached. Both sides of the differential output pair
should either be left floating or terminated.
20%
80%
80%
20%
t
R
t
F
V
OUT
nQ0:nQ3
Q0:Q3
V
IN
, V
OUT
800mV
(typical)
V
DIFF_IN
, V
DIFF_OUT
1600mV
(typical)
tsw
nQ0:nQ3
Q0:Q3
SEL
IN2
IN1
nQ0:nQ3
Q0:Q3
9©2017 Integrated Device Technology, Inc. September 22, 2017
8S89834I Datasheet
VFQFN EPAD Thermal Release Path
In order to maximize both the removal of heat from the package and
the electrical performance, a land pattern must be incorporated on
the Printed Circuit Board (PCB) within the footprint of the package
corresponding to the exposed metal pad or exposed heat slug on the
package, as shown in Figure 2. The solderable area on the PCB, as
defined by the solder mask, should be at least the same size/shape
as the exposed pad/slug area on the package to maximize the
thermal/electrical performance. Sufficient clearance should be
designed on the PCB between the outer edges of the land pattern
and the inner edges of pad pattern for the leads to avoid any shorts.
While the land pattern on the PCB provides a means of heat transfer
and electrical grounding from the package to the board through a
solder joint, thermal vias are necessary to effectively conduct from
the surface of the PCB to the ground plane(s). The land pattern must
be connected to ground through these vias. The vias act as “heat
pipes”. The number of vias (i.e. “heat pipes”) are application specific
and dependent upon the package power dissipation as well as
electrical conductivity requirements. Thus, thermal and electrical
analysis and/or testing are recommended to determine the minimum
number needed. Maximum thermal and electrical performance is
achieved when an array of vias is incorporated in the land pattern. It
is recommended to use as many vias connected to ground as
possible. It is also recommended that the via diameter should be 12
to 13mils (0.30 to 0.33mm) with 1oz copper via barrel plating. This is
desirable to avoid any solder wicking inside the via during the
soldering process which may result in voids in solder between the
exposed pad/slug and the thermal land. Precautions should be taken
to eliminate any solder voids between the exposed heat slug and the
land pattern. Note: These recommendations are to be used as a
guideline only. For further information, please refer to the Application
Note on the Surface Mount Assembly of Amkor’s Thermally/
Electrically Enhance Leadframe Base Package, Amkor Technology.
Figure 2. P.C. Assembly for Exposed Pad Thermal Release Path – Side View (drawing not to scale)
SOLDERSOLDER
PINPIN EXPOSED HEAT SLUG
PIN PAD PIN PADGROUND PLANE LAND PATTERN
(GROUND PAD)
THERMAL VIA

8S89834AKILFT

Mfr. #:
Manufacturer:
IDT
Description:
Clock Drivers & Distribution SMALL SIGE ARRAY
Lifecycle:
New from this manufacturer.
Delivery:
DHL FedEx Ups TNT EMS
Payment:
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