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NCP1031DR2

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NCP1030, NCP1031
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13
OPERATING DESCRIPTION
Introduction
The NCP1030 and NCP1031 are a family of miniature
monolithic voltage−mode switching regulators designed for
isolated and non−isolated bias supply applications. The
internal startup circuit and the MOSFET are rated at 200 V,
making them ideal for 48 V telecom and 42 V automotive
applications. In addition, the NCP103x family can operate
from an existing 12 V supply. This controller family is
optimized for operation up to 1 MHz.
The NCP103x family incorporates in a single IC all the
active power, control logic and protection circuitry required
to implement, with a minimum of external components,
several switching regulator applications, such as a
secondary side bias supply or a low power dc−dc converter.
The NCP1030 is available in the space saving Micro8t
package and is targeted for applications requiring up to 3 W.
The NCP1031 is targeted for applications up to 6 W and is
available in the SO−8 package.
The NCP103x includes an extensive set of features
including over temperature protection, cycle by cycle
current limit, individual line under and overvoltage
detection comparators with hysteresis, and regulator output
undervoltage lockout with hysteresis, providing full
protection during fault conditions. A description of each of
the functional blocks is given below, and the representative
block diagram is shown in Figure 2.
Startup Circuit and Undervoltage Lockout
The NCP103x contains an internal 200 V startup regulator
that eliminates the need for external startup components.
The startup regulator consists of a constant current source
that supplies current from the input line (V
in
) to the capacitor
on the V
CC
pin (C
CC
). Once the V
CC
voltage reaches
approximately 10 V, the startup circuit is disabled and the
Power Switch Circuit is enabled if no faults are present.
During this self−bias mode, power to the NCP103x is
supplied by the V
CC
capacitor. The startup regulator turns
ON again once V
CC
reaches 7.5 V. This “7.5−10” mode of
operation is known as Dynamic Self Supply (DSS). The
NCP1030 and NCP1031 startup currents are 12 mA and 16
mA, respectively.
If V
CC
falls below 7.5 V, the device enters a re−start mode.
While in the re−start mode, the V
CC
capacitor is allowed to
discharge to 6.5 V while the Power Switch is enabled. Once
the 6.5 V threshold is reached, the Power Switch Circuit is
disabled and the startup regulator is enabled to charge the
V
CC
capacitor. The Power Switch is enabled again once the
V
CC
voltage reaches 10 V. Therefore, the external V
CC
capacitor must be sized such that a voltage greater than 7.5
V is maintained on the V
CC
capacitor while the converter
output reaches regulation. Otherwise, the converter will
enter the re−start mode. Equation (1) provides a guideline
for the selection of the V
CC
capacitor for a forward
converter;
Forward:
(eq. 1
)
C
CC
+
cos
−1
ǒ
1 *
V
OUT@
N
P
DC@V
in
@N
S
Ǔ
L
OUT
C
OUT
Ǹ
@ I
bias
2.6
where, I
bias
is the bias current supplied by the V
CC
capacitor
including the IC bias current (I
CC1
) and any additional
current used to bias the feedback resistors (if used).
After initial startup, the V
CC
pin should be biased above
V
CC(off)
using an auxiliary winding. This will prevent the
startup regulator from turning ON and reduce power
dissipation. Also, the load should not be directly connected
to the V
CC
capacitor. Otherwise, the load may override the
startup circuit. Figure 33 shows the recommended
configuration for a non−isolated flyback converter.
Figure 33. Non−Isolated Bias Supply Configuration
GND
COMP
+
V
in
−
VCC
VDRAIN
UV
OV
CT
VFB
NCP103x
+
V
out
−
The maximum voltage rating of the startup circuit is
200 V. Power dissipation should be observed to avoid
exceeding the maximum power dissipation of the package.
Error Amplifier
The internal error amplifier (EA) regulates the output
voltage of the bias supply. It compares a scaled output
voltage signal to an internal 2.5 V reference (V
REF
)
connected to its non−inverting input. The scaled signal is fed
into the feedback pin (
V
FB
) which is the inverting input of the
error amplifier.
The output of the error amplifier is available for frequency
compensation and connection to the PWM comparator
through the COMP pin. To insure normal operation, the EA
compensation should be selected such that the EA frequency
response crosses 0 dB below 80 kHz.
The error amplifier input bias current is less than 1 mA
over the operating range. The output source and sink
currents are typically 110 mA and 550 mA, respectively.
Under load transient conditions, COMP may need to
move from the bottom to the top of the C
T
Ramp. A large
current is required to complete the COMP swing if small
resistors or large capacitors are used to implement the
compensation network. In which case, the COMP swing will
NCP1030, NCP1031
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14
be limited by the EA sink current, typically 110 mA.
Optimum transient response is obtained if the compensation
components allow COMP to swing across its operating
range in 1 cycle.
Line Under and Overvoltage Detector
The NCP103x incorporates individual line undervoltage
(UV) and overvoltage (OV) shutdown circuits. The UV and
OV thresholds are 2.5 V. A fault is present if the UV is below
2.5 V or if the OV voltage is above 2.5 V. The UV/OV
detectors incorporate 175 mV hysteresis to prevent noise
from triggering the shutdown circuits.
The UV/OV circuits can be biased using an external
resistor divider from the input line as shown in Figure 34.
The UV/OV pins should be bypassed using a capacitor to
prevent triggering the UV or OV circuits during normal
switching operation.
Figure 34. UV/OV Resistor Divider
from the Input Line
R
1
R
2
R
3
V
in
V
UV
−
+
V
OV
−
+
The resistor divider must be sized to enable the controller
once V
in
is within the required operating range. While a UV
or OV fault is present, switching is not allowed and the
COMP pin is effectively grounded.
Either of these comparators can be used for a different
function if UV or OV functions are not needed. For example,
the UV/OV detectors can be used to implement an enable or
disable function. If positive logic is used, the enable signal
is applied to the UV pin while the OV pin is grounded. If
negative logic is used, the disable signal is applied to the OV
pin while biasing the UV pin from V
CC
using a resistor
divider.
Oscillator
The oscillator is optimized for operation up to 1 MHz and
its frequency is set by the external timing capacitor (C
T
)
connected to the C
T
pin. The oscillator has two modes of
operation, free running and synchronized (sync). While in
free running mode, an internal current source sequentially
charges and discharges C
T
generating a voltage ramp
between 3.0 V and 3.5 V. Under normal operating
conditions, the charge (I
CT(C)
) and discharge (I
CT(D)
)
currents are typically 215 mA and 645 mA, respectively. The
charge:discharge current ratio of 1:3 discharges
C
T
in 25 %
of the total period. The Power Switch is disabled while C
T
is discharging, guaranteeing a maximum duty cycle of 75 %
as shown in Figure 35.
25 %
Max
Duty Cycle
COMP
75%
Figure 35. Maximum Duty Cycle vs COMP
C
T
Ramp
Power Switch
Enabled
C
T
Charge
Signal
Figure 18 shows the relationship between the operating
frequency and C
T
. If an UV fault is present, both I
CT(C)
and
I
CT(D)
are reduced by a factor of 7, thus reducing the
operating frequency by the same factor.
The oscillator can be synchronized to a higher frequency
by capacitively coupling a synchronization pulse into the C
T
pin. In sync mode, the voltage on the C
T
pin needs to be
driven above 3.5 V to trigger the internal comparator and
complete the C
T
charging period. However, pulsing the C
T
pin before it reaches 3.5 V will reduce the p−p amplitude of
the C
T
Ramp as shown in Figure 36.
Figure 36. External Frequency Synchronization
Waveforms
3.0 V
3.5 V
Sync Pulse
3.0 V/3.5 V
Comparator
Reset
Free Running
Mode
Sync Mode
T1 (f1) T2 (f2)
T2 (f2)
C
T
Ramp
C
T
Voltage
Range in Sync
The oscillator frequency should be set no more that 25%
below the target sync frequency to maintain an adequate
voltage range and provide good noise immunity. A possible
circuit to synchronize the oscillator is shown in Figure 37.
2
5 V
C1
R1
R2
Figure 37. External Frequency Synchronization
Circuit.
C
T
C
T
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PWM Comparator and Latch
The Pulse Width Modulator (PWM) Comparator
compares the error amplifier output (COMP) to the C
T
Ramp and generates a proportional duty cycle. The Power
Switch is enabled while the C
T
Ramp is below COMP as
shown in Figure 35. Once the C
T
Ramp reaches COMP, the
Power Switch is disabled. If COMP is at the bottom of the
C
T
Ramp, the converter operates at minimum duty cycle.
While COMP increases, the duty cycle increases, until
COMP reaches the peak of the C
T
Ramp, at which point the
controller operates at maximum duty cycle.
The C
T
Charge Signal is filtered through a One Shot Pulse
Generator to set the PWM Latch and enable switching at the
beginning of each period. Switching is allowed while the C
T
Ramp is below COMP and a current limit fault is not present.
The PWM Latch and Comparator propagation delay is
typically 150 ns. If the system is designed to operate with a
minimum ON time less than 150 ns, the converter will skip
pulses. Skipping pulses is usually not a problem, unless
operating at a frequency close to the audible range. Skipping
pulses is more likely when operating at high frequencies
during high line and minimum load condition.
A series resistor is included for ESD protection between the
EA output and the COMP pin. Under normal operation, a 220
mV offset is observed between the C
T
Ramp and the COMP
crossing points. This is not a problem as the series resistor
does not interact with the error amplifier transfer function.
Current Limit Comparator and Power Switch Circuit
The NCP103x monolithically integrates a 200 V Power
Switch Circuit with control logic circuitry. The Power
Switch Circuit is designed to directly drive the converter
transformer. The characteristics of the Power Switch Circuit
are well known. Therefore, the gate drive is tailored to
control switching transitions and help limit electromagnetic
interference (EMI). The Power Switch Circuit is capable of
switching 200 V.
The Power Switch Circuit incorporates SENSEFET™
technology to monitor the drain current. A sense voltage is
generated by driving a sense element, R
SENSE
, with a current
proportional to the drain current. The sense voltage is
compared to an internal reference voltage on the
non−inverting input of the Current Limit Comparator. If the
sense voltage exceeds the reference level, the comparator
resets the PWM Latch and switching is terminated. The
NCP1030 and NCP1031 drain current limit thresholds are
0.5 A and 1.0 A, respectively.
Each time the Power Switch Circuit turns ON, a narrow
voltage spike appears across R
SENSE
. The spike is due to the
Power Switch Circuit gate to source capacitance,
transformer interwinding capacitance, and output rectifier
recovery time. This spike can cause a premature reset of the
PWM Latch. A proprietary active Leading Edge Blanking
(LEB) Circuit masks the current signal to prevent the
voltage spike from resetting the PWM Latch. The active
LEB masks the current signal until the Power Switch turn
ON transition is complete. The adaptive LEB period
provides better current limit control compared to a fixed
blanking period.
The current limit propagation delay time is typically
100 ns. This time is measured from when an overcurrent
fault appears at the Power Switch Circuit drain, to the start
of the turn−off transition. Propagation delay must be
factored in the transformer design to avoid transformer
saturation.
Thermal Shutdown
Internal Thermal Shutdown circuitry is provided to
protect the integrated circuit in the event the maximum
junction temperature is exceeded. When activated, typically
at 150_C, the Power Switch Circuit is disabled. Once the
junction temperature falls below 105_C, the NCP103x is
allowed to resume normal operation. This feature is
provided to prevent catastrophic failures from accidental
device overheating. It is not intended to be used as a
substitute for proper heatsinking.
Application Considerations
A 2 W bias supply for a 48 V telecom system was designed
using the NCP1030. The bias supply generates an isolated
12 V output. The circuit schematic is shown in Figure 38.
Application Note AND8119/D describes the design of the
bias supply.
Figure 38. 2 W Isolated Bias Supply Schematic
GND
COMP
+
35−76V
−
VCC
VDRAIN
UV
OV
CT
VFB
+
−
22
MBRA160T3
MBRA160T3
2.2
1M
10
4k99
1k30
10k
0.033
680p
680p
0.01
0.01
2.2
2.2
1:2.78
45k3
34k
12V
NCP1030
0.022
100 p
MURA110T3
499
VCC Excursion and Compensation
Some applications may regulate nodes that are not directly
connected to VCC, such as the secondary or AUX1 shown
in Figure 39. The regulation of another node can result in
loose regulation of VCC. The result of loose regulation is
that VCC can rise to unacceptable levels when a heavy load
is applied to the regulated node and a relatively light load is
applied to the VCC pin. The large voltage can lead to
damage of the NCP1030/31 or other downstream parts.
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NCP1031DR2

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IC CTRLR PWM OTP OVD HV 8SOIC
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