AD648
REV. E
–9–
TEMP R
SH
V
OS
I
B
ⴗC(M⍀)(V) (1 + R
F
/R
SH
) V
OS
(pA) I
B
R
F
TOTAL
–25 15,970 150 151 V 0.30 30 V 181 V
0 2,830 225 233 V 2.26 262 V 495 V
+25 500 300 360 V 10.00 1.0 mV 1.36 mV
+50 88.5 375 800 V 56.6 5.6 mV 6.40 mV
+75 15.6 450 3.33 mV 320 32 mV 35.3 mV
+85 7.8 480 6.63 mV 640 64 mV 70.6 mV
Figure 28. Photodiode Pre-Amp Errors Over Temperature
DUAL PHOTODIODE PREAMP
The performance of the dual photodiode preamp shown in
Figure 27 is enhanced by the AD648’s low input current, input
voltage offset, and offset voltage drift. Each photodiode sources
a current proportional to the incident light power on its surface.
R
F
converts the photodiode current to an output voltage equal
to R
F
× I
S
.
An error budget illustrating the importance of low amplifier
input current, voltage offset, and offset voltage drift to minimize
output voltage errors can be developed by considering the
equivalent circuit for the small (0.2 mm
2
area) photodiode
shown in Figure 27. The input current results in an error pro-
portional to the feedback resistance used. The amplifier’s offset
will produce an error proportional to the preamp’s noise gain
(1+R
F
/R
SH
), where R
SH
is the photodiode shunt resistance. The
amplifier’s input current will double with every 10°C rise in
temperature, and the photodiode’s shunt resistance halves with
every 10°C rise. The error budget in Figure 28 assumes a room
temperature photodiode R
SH
of 500 MΩ, and the maximum
input current and input offset voltage specs of an AD648C.
The capacitance at the amplifier’s negative input (the sum of the
photodiode’s shunt capacitance, the op amp’s differential input
capacitance, stray capacitance due to wiring, etc.) will cause a
rise in the preamp’s noise gain over frequency. This can result in
excess noise over the bandwidth of interest. C
F
reduces the
noise gain “peaking” at the expense of signal bandwidth.
Figure 27. A Dual Photodiode Pre-Amp
The AD648 in this configuration provides a 700 kHz small signal
bandwidth and 1.8 V/µs typical slew rate. The 33 pF capacitor
across the feedback resistor optimizes the circuit’s response. The
oscilloscope photos in Figures 26a and 26b show small and
large signal outputs of the circuit in Figure 24. Upper traces
show the input signal V
IN
. Lower traces are the resulting output
voltage with the DAC’s digital input set to all 1s. The circuit
settles to ±0.01% for a 20 V input step in 14 µs.
Figure 26a. Response to
±
20 V p-p Reference Square
Wave
Figure 26b. Response to
±
100 mV p-p Reference Square
Wave
