288 Pin DDR4 1.2V 2400 ECC UDIMM
8GB Based on 1Gx8
AQD-D4U8GE24-SE
Advantech
2
2
Description
DDR4 1.2V ECC Unbuffered DIMM is high-speed, low
power memory module that use 1Gx8bits DDR4 SDRAM
in FBGA package and a 4096 bits serial EEPROM on a
288-pin printed circuit board. DDR4 1.2V Unbuffered
DIMM is a Dual In-Line Memory Module and is intended
for mounting into 288-pin edge connector sockets.
Synchronous design allows precise cycle control with the
use of system clock. Data I/O transactions are possible
on both edges of DQS. Range of operation frequencies,
programmable latencies allow the same device to be
useful for a variety of high bandwidth, high performance
memory system applications.
Features
RoHS compliant products
JEDEC standard 1.2V (1.14V to 1.26V) Power supply
VDDQ=1.2V (1.14V to 1.26V)
Clock Freq: 1200MHZ for 2400Mb/s/Pin
16 Banks (4 Bank Groups)
Programmable CAS Latency: 10, 11, 12, 13, 14,15,16,
17,18
Programmable Additive Latency (Posted /CAS):
0,CL-2 or CL-1 clock
Programmable /CAS Write Latency (CWL)
= 12,16 (DDR4-2400)
8 bit pre-fetch
Burst Length: 4, 8
Bi-directional Differential Data-Strobe
On Die Termination with ODT pin
Serial presence detect with EEPROM
Asynchronous reset
PCB: 30µ gold finger
Pin Identification
Symbol Function
A0–A17 Register address input
BA0, BA1 Register bank select input
BG0, BG1 Register bank group select input
RAS_n2 Register row address strobe input
CAS_n3 Register column address strobe input
WE_n4 Register write enable input
CS0_n, CS1_n,
CS2_n, CS3_n
DIMM Rank Select Lines input
CKE0, CKE1 Register clock enable lines input
ODT0, ODT1
Register on-die termination control lines
input
ACT_n Register input for activate input
DQ0–DQ63 DIMM memory data bus
CB0–CB7 DIMM ECC check bits
DQS0_t–
DQS17_t
Data Buffer data strobes (positive line
of differential pair)
DQS0_c–
DQS17_c
Data Buffer data strobes (negative line
of differential pair)
CK0_t, CK1_t
Register clock input (positive line of
differential pair)
CK0_c, CK1_c
Register clocks input (negative line of
differential pair)
SCL
I2C serial bus clock for SPD/TS and
register
SDA
I2C serial bus data line for SPD/TS and
register
SA0–SA2
I2C slave address select for SPD/TS
and register
