OMO ElectronicOMO Electronic
Expand menu
Hello, Sign inMy Account
0 Cart

AQD-D4U8GE24-SE

P1-P3P4-P6P7-P9P10-P12P13-P15
288 Pin DDR4 1.2V 2400 ECC UDIMM
8GB Based on 1Gx8
AQD-D4U8GE24-SE
Advantech
10
1
CAS_n to CAS_n command delay for
different bank group
tCCD_S
4 nCK
Auto precharge write recovery +
precharge time
tDAL(min)
Programmed WR + roundup ( tRP / tCK(avg)) nCK
ACTIVATE to ACTIVATE Command
delay to different bank group for 2KB
page size
tRRD_S(2K) Max(4nCK,5 .3ns)
- nCK
Parameter Symbol Min Max Unit
ACTIVATE to ACTIVATE Command
delay to different bank group for 1KB
page size
RRD_S(1K) Max(4nCK,3 .3ns)
- nCK
ACTIVATE to ACTIVATE Command
delay to different bank group for 1/ 2KB
page size
tRRD_S(1/
2K)
Max(4nCK,3 .3ns)
nCK
ACTIVATE to ACTIVATE Command
delay to same bank group for 2KB page
size
tRRD_L(2K) Max(4nCK,6 .4ns)
nCK
ACTIVATE to ACTIVATE Command
delay to same bank group for 1KB page
size
tRRD_L(1K) Max(4nCK,4 .9ns)
nCK
ACTIVATE to ACTIVATE Command
delay to same bank group for 1/2KB
page size
tRRD_L(1/
2K)
Max(4nCK,4 .9ns)
nCK
Four activate window for 2KB page size
tFAW_2K Max(28nCK, 30ns) - ns
Four activate window for 1KB page size
tFAW_1K Max(20nCK, 21ns) ns
Four activate window for 1/2KB page
size
tFAW_1/2K Max(16nCK, 13ns) - ns
Power-up and RESET calibration time
tZQinitl
1024 - nCK
Normal operation Full calibration time tZQoper
512 -
nCK
Normal operation short calibration time tZQcs 128
- nCK
Exit self refresh to commands not
requiring a locked DLL
tXS tRFC(min)+ 10ns
-
Exit self refresh to commands requiring a
locked DLL
tXSDLL tDLLK(min)
-
Internal read to precharge command
delay
tRTP max (4nCK,7.5ns )
-
Minimum CKE low width for Self refresh
entry to exit timing
tCKESR tCKE(min)+ 1nCK
-
Exit power down with DLL to any valid
command: Exit Precharge Power Down
with DLL
tXP max (4nCK,6ns)
-
CKE minimum pulse width (high and low
pulse width)
tCKE max (3nCK, 5ns)
Asynchronous RTT turn-on delay
(Power-Down with DLL frozen)
tAONAS 1.0 9.0
ns
Asynchronous RTT turn-off delay
(Power-Down with DLL frozen)
tAOFAS
1.0 9.0 ns
RTT dynamic change skew tADC
0.3 0.7 ns
288 Pin DDR4 1.2V 2400 ECC UDIMM
8GB Based on 1Gx8
AQD-D4U8GE24-SE
Advantech
11
1
SERIAL PRESENCE DETECT SPECIFICATION
8192MB(1024Mx72Bit ) Serial Presence Detect for DDR4 ECC DIMM (PC-19200) 2400 CL=17
BYTE FUNCTION DESCRIDED FUNCTION SUPPORTED HEX VALUE
0 Number of serial PD bytes written/SPD device size/CRC coverage 512B Total, 384B Used 23
1 SPD revision Revision 1.0 10
2 Key byte/DRAM device type DDR4 SDRAM 0C
3 Key byte/module type UDIMM 02
4 SDRAM density and banks 8Gb, 4BG, 4Banks 85
5 SDRAM addressing 16 rows, 10 columns 21
6 SDRAM package type Monolithic DRAM Device 00
7 SDRAM optional features Unlimited MAC 08
8 SDRAM thermal and refresh options — 00
9 Other SDRAM optional feature sPPR supported 60
10 Reserved — 00
11 Module Nominal Voltage,VDD 1.2V 03
12 Module organization 1Ranks / x8 bits 01
13 Module memory bus width 72 bits / with ECC 0B
14 Module thermal sensor Incorporated 80
15 Reserved — 00
16 Reserved — 00
17 Timebases MTB 125ps, FTB 1ps 00
18 SDRAM minimum cycle time(tCKAVG min) 0.833ns 07
19 SDRAM maximum cycle time(tCKAVG max) 1.5ns 0C
20 CAS latencies supported, first byte CL=10,11,12,13,14,15,16,17,18 F8
21 CAS latencies supported, second byte CL=10,11,12,13,14,15,16,17,18 0F
22 CAS latencies supported, third byte CL=10,11,12,13,14,15,16,17,18 00
23 CAS latencies supported, fourth byte CL=10,11,12,13,14,15,16,17,18 00
24 Minimum CAS latency time(tAA min) 13.75ns 6E
25 Minimum RAS to CAS delay time(tRCD min) 13.75ns 6E
26 Minimum Row precharge delay time(tRP min) 13.75ns 6E
288 Pin DDR4 1.2V 2400 ECC UDIMM
8GB Based on 1Gx8
AQD-D4U8GE24-SE
Advantech
12
1
27 Upper nibbles for tRAS min and tRC min tRAS = 32ns, tRC = 45.75ns 11
28 Minimum active to precharge delay time(tRAS min), least significant byte 32ns 00
29 Minimum active to active/refresh delay time(tRC min), least significant byte 45.75ns 6E
30 Minimum refresh recovery delay time(tRFC1 min), LSB 350ns F0
31 Minimum refresh recovery delay time(tRFC1 min), MSB 350ns 0A
32 Minimum refresh recovery delay time(tRFC2 min), LSB 260ns 20
33 Minimum refresh recovery delay time(tRFC2 min), MSB 260ns 08
34 Minimum refresh recovery delay time(tRFC3 min), LSB 160ns 00
35 Minimum refresh recovery delay time(tRFC3 min), MSB 160ns 05
36 Minimum four activate window time(tFAW min), most significant nibble 21ns 00
37 Minimum four activate window time(tFAW min), least significant byte 21ns A8
38 Minimum activate to activate delay time(tRRD_S min), different bank group 3.3ns 1B
39 Minimum activate to activate delay time(tRRD_L min), same bank group 4.9ns 28
40 Minimum CAS to CAS delay time(tCCD_L min), same bank group 5ns 28
41 Upper Nibble for tWR min 15ns 00
42 Minimum Write Recovery Time (tWR min) 15ns 78
43 Upper Nibbles for tWTR min 2.5ns 00
44 Minimum Write to Read Time (tWTR_S min), different bank group 2.5ns 14
45 Minimum Write to Read Time (tWTR_L min), same bank group 7.5ns 3C
46~59 Reserved — 00
60 Connector to SRAM bit mapping DQ0 - 3 16
61 Connector to SRAM bit mapping DQ4 - 7 36
62 Connector to SRAM bit mapping DQ8 - 11 16
63 Connector to SRAM bit mapping DQ12 - 15 36
64 Connector to SRAM bit mapping DQ16 - 19 16
65 Connector to SRAM bit mapping DQ20 - 23 36
66 Connector to SRAM bit mapping DQ24 - 27 16
67 Connector to SRAM bit mapping DQ28 - 31 36
68 Connector to SRAM bit mapping CB0 - 3 16
P1-P3P4-P6P7-P9P10-P12P13-P15

AQD-D4U8GE24-SE

Mfr. #:
Buy AQD-D4U8GE24-SE
Manufacturer:
Advantech
Description:
Memory Modules 8G ECC DDR4-2400 1GX8 1.2V SAM
Lifecycle:
New from this manufacturer.
Delivery:
DHL FedEx Ups TNT EMS
Payment:
T/T Paypal Visa MoneyGram Western Union

Products related to this Datasheet