Philips Semiconductors
PCF85102C-2
256 × 8-bit CMOS EEPROM with I
2
C-bus interface
Product data Rev. 04 — 22 October 2004 11 of 20
9397 750 14216
© Koninklijke Philips Electronics N.V. 2004. All rights reserved.
11. I
2
C-bus characteristics
[1] The hold time required (not greater than 300 ns) to bridge the undefined region of the falling edge of SCL must be internally provided by
a transmitter.
Table 8: I
2
C-bus characteristics
All of the timing values are valid within the operating supply voltage and ambient temperature range and refer to V
IL
and V
IH
with an input voltage swing from V
SS
to V
DD
; see Figure 9.
Symbol Parameter Conditions Min Max Unit
f
SCL
clock frequency 0 100 kHz
t
BUF
bus free time between a STOP and
START condition
4.7 −µs
t
HD;STA
START condition hold time after
which first clock pulse is generated
4.0 −µs
t
LOW
LOW level clock period 4.7 −µs
t
HIGH
HIGH level clock period 4.0 −µs
t
SU;STA
set-up time for START condition repeated start 4.7 −µs
t
HD;DAT
data hold time
for bus compatible masters 5 −µs
for bus devices
[1]
0 − ns
t
SU;DAT
data set-up time 250 − ns
t
r
SDA and SCL rise time − 1 µs
t
f
SDA and SCL fall time − 300 ns
t
SU;STO
set-up time for STOP condition 4.0 −µs
P = STOP condition; S = START condition.
Fig 9. Timing requirements for the I
2
C-bus.
MBA705
t
BUF
HD;STA
t
SCL
SDA
P S
t
LOW
t
r
HD;DAT
t
SU;DAT
t
t
f
t
HIGH
S
HD;STA
t
SU;STA
t
SU;STO
t
P
