Data Sheet ADuM7640/ADuM7641/ADuM7642/ADuM7643
Rev. 0 | Page 17 of 20
APPLICATIONS INFORMATION
PRINTED CIRCUIT BOARD LAYOUT
The ADuM7640/ADuM7641/ADuM7642/ADuM7643 digital
isolators require no external interface circuitry for the logic
interfaces. Power supply bypassing is strongly recommended at the
input and output supply pins (see Figure 20). Connect four bypass
capacitors between Pin 1 and Pin 2 for V
DD1A
, between Pin 7 and
Pin 10 for V
DD1B
, between Pin 11 and Pin 14 for V
DD2B
, and between
Pin 19 and Pin 20 for V
DD2A
. Connect the V
DD1A
supply pin and the
V
DD1B
supply pin together, and connect the V
DD2B
supply pin and
V
DD2A
supply pin together. The capacitor values should be from
0.01 µF to 0.1 µF. The total lead length between both ends of the
capacitor and the power supply pin should not exceed 20 mm.
V
DD1A
GND
1
V
IA
V
IB
V
IC
/V
OC
V
ID
/V
OD
V
DD1B
V
IE
/V
OE
V
IF
GND
1
V
DD2A
GND
2
V
OA
V
OB
V
OC
/V
IC
V
OD
/V
ID
V
DD2B
V
OE
/V
IE
V
OF
GND
2
10448-020
Figure 20. Recommended Printed Circuit Board Layout
In applications involving high common-mode transients, it is
important to minimize board coupling across the isolation barrier.
Furthermore, users should design the board layout so that any
coupling that occurs affects all pins equally on a given component
side. Failure to follow this design guideline can cause voltage
differentials between pins that exceed the absolute maximum
ratings of the device, which can lead to latch-up or permanent
damage.
With proper PCB design choices, the ADuM7640/ADuM7641/
ADuM7642/ADuM7643 can readily meet CISPR 22 Class A
(and FCC Class A) emissions standards, as well as the more
stringent CISPR 22 Class B (and FCC Class B) standards in
an unshielded environment. For PCB-related EMI mitigation
techniques, including board layout and stack-up issues, see the
AN-1109 Application Note.
PROPAGATION DELAY-RELATED PARAMETERS
Propagation delay is a parameter that describes the time it takes
a logic signal to propagate through a component. The input-to-
output propagation delay time for a high-to-low transition may
differ from the propagation delay time for a low-to-high transition.
INPUT (V
Ix
)
OUTPUT (V
Ox
)
t
PLH
t
PHL
50%
50%
10448-021
Figure 21. Propagation Delay Parameters
Pulse width distortion is the maximum difference between these
two propagation delay values and is an indication of how accurately
the timing of the input signal is preserved.
Channel-to-channel matching refers to the maximum amount
of time that the propagation delay differs between channels
within a single ADuM7640/ADuM7641/ADuM7642/ADuM7643
component.
Propagation delay skew refers to the maximum amount of time
that the propagation delay differs between multiple ADuM7640/
ADuM7641/ADuM7642/ADuM7643 components operating
under the same conditions.
DC CORRECTNESS
Positive and negative logic transitions at the isolator input
cause narrow (~1 ns) pulses to be sent to the decoder using the
transformer. The decoder is bistable and is, therefore, either set
or reset by the pulses, indicating input logic transitions. In the
absence of logic transitions at the input for more than ~1 µs, a
periodic set of refresh pulses indicative of the correct input state
is sent to ensure dc correctness at the output. If the decoder receives
no internal pulses for more than approximately 5 µs, the input side
is assumed to be unpowered or nonfunctional, in which case the
isolator output is forced to a default high state by the watchdog
timer circuit.
