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NB6L14SMNTXG

P1-P3P4-P6P7-P9P10-P11
NB6L14S
http://onsemi.com
7
TIME (58 ps/div)
Figure 9. Typical Output Waveform at 2.488 Gb/s with PRBS 2
23−1
and OC48 mask
(V
INPP
= 100 mV; Input Signal DDJ = 14 ps)
VOLTAGE (63.23 mV/div)
Device DDJ = 10 ps
V
CC
= 3.3 V or 2.5 V
LVPECL
Driver
IN
50 W
Z
o
= 50 W
Z
o
= 50 W
50 W
IN
NB6L14S
V
CC
= 2.5 V
Figure 10. LVPECL Interface
V
T
= V
CC
− 2.0 V
V
EE
/ GND GND
V
CC
= 3.3 V or 2.5 V
LVPECL
Driver
IN
50 W
Z
o
= 50 W
Z
o
= 50 W
50 W
IN
NB6L14S
V
CC
= 2.5 V
Figure 11. LVPECL Y−Termination Interface
V
T
V
EE
/ GND GNDGND
V
CC
0.1 mF
19 W
Figure 12. LVDS Interface
LVDS
Driver
IN
50 W
Z
o
= 50 W
Z
o
= 50 W
50 W
IN
V
T
= OPEN
GND GND
NB6L14S
V
CC
= 3.3 V or 2.5 V V
CC
= 2.5 V
Figure 13. CML Interface
CML
Driver
IN
50 W
Z
o
= 50 W
Z
o
= 50 W
50 W
IN
V
T
= V
CC
GND GND
NB6L14S
V
CC
= 2.5 V V
CC
= 2.5 V
NB6L14S
http://onsemi.com
8
Figure 14. HSTL Interface
HSTL
Driver
IN
50 W
Z
o
= 50 W
Z
o
= 50 W
50 W
IN
V
T
= GND
GND GND
NB6L14S
V
CC
= 3.3 V or 2.5 V V
CC
= 2.5 V
GND
V
CC
= 2.5 V
GND
LVCMOS
Driver
50 W*
Z
o
= 50 W
50 W*
NB6L14S
Figure 15. LVCMOS Interface
IN
V
T
= OPEN
IN
GND
V
CC
= 2.5 V
2.5 kW
V
CC
Differential
Driver
IN
50 W
Z
o
= 50 W
Z
o
= 50 W
50 W
IN
V
CC
= 2.5 V
V
T
= V
REFAC
*
V
CC
Single−Ended
Driver
IN
50 W
Z
o
= 50 W
50 W
IN
GND GND
GND GND
V
T
= V
REFAC
*
NB6L14S
NB6L14S
V
CC
= 2.5 V
GNDGND
LVTTL
Driver
50 W*
Z
o
= 50 W
50 W*
NB6L14S
Figure 16. LVTTL Interface
IN
V
T
= OPEN
IN
*V
REFAC
bypassed to ground with a 0.1 mF capacitor.
V
CC
= 2.5 V V
CC
= 2.5 V
GND
1.5 kW
Figure 17. Capacitor−Coupled Differential
Interface (V
T
Connected to V
REF_AC
)
Figure 18. Capacitor−Coupled Single−Ended Interface (V
T
Connected to V
REFAC
)
*V
REFAC
bypassed to ground with a 0.1 mF capacitor.
NB6L14S
http://onsemi.com
9
Figure 19. AC Reference Measurement
IN
IN
Q
Q
t
PHL
t
PLH
V
INPP
= V
IH
(D) − V
IL
(D)
V
OUTPP
= V
OH
(Q) − V
OL
(Q)
Figure 20. Typical LVDS Termination for Output Driver and Device Evaluation
Driver
Device
Oscilloscope
QD
Q D
LVDS
100 W
Z
o
= 50 W
Z
o
= 50 W
HI Z Probe
HI Z Probe
V
OL
Q
N
V
OH
Q
N
V
OS
V
OD
Figure 21. LVDS Output
Figure 22. Differential Input Driven
Single−Ended
IN
Figure 23. Differential Inputs Driven
Differentially
IN
V
th
V
th
IN
IN
V
IH
V
IL
V
IHmax
V
ILmax
V
IHmin
V
ILmin
V
CC
V
thmax
V
thmin
GND
V
th
Figure 24. V
th
Diagram
IN
IN
V
ILD(MAX)
V
IHD(MAX)
V
IHD
V
ILD
V
IHD(MIN)
V
ILD(MIN)
V
CMR
GND
Figure 25. V
CMR
Diagram
V
ID
= V
IHD
− V
ILD
V
CC
V
CMRmax
V
CMRmin
P1-P3P4-P6P7-P9P10-P11

NB6L14SMNTXG

Mfr. #:
Buy NB6L14SMNTXG
Manufacturer:
ON Semiconductor
Description:
Clock Buffer CZ4 DIFF IN LVDS OUT
Lifecycle:
New from this manufacturer.
Delivery:
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