COMMERCIAL TEMPERATURE RANGE
IDTCV183-2A
PROGRAMMABLE FLEXPC CLOCK FOR P4 PROCESSOR
11
BYTE 11
BYTE 14 RESERVED
BYTE 13
Bit Output(s) Affected Description / Function 0 1 Type Power On
7 48M Strength control 1 1.2 RW 1
6 REF Strength control 1 1.2 RW 1
5 PCIF5 Strength control 1 1.2 RW 0
4 PCI4 Strength control 1 1.2 RW 0
3 PCI3 Strength control 1 1.2 RW 0
2 PCI2 Strength control 1 1.2 RW 0
1 PCI1 Strength control 1 1.2 RW 0
0 PCI0 Strength control 1 1.2 RW 0
Bit Output(s) affected Description/ Function 0 1 Type Power On
7 SRC5_EN_Strap R
The latch of
SRC5_EN
6 PLL3 PLL3 enable PLL3 pwr dwn Pwr up RW
1
5 PLL2 PLL2 enable PLL2 pwr dwn Pwr up RW
1
4 SRC_DIV SRC divider disable disable enable RW
1
3 PCI_DIV PCI divider disable disable enable RW
1
2 CPU_DIV CPU divider disable disable enable RW
1
1 CPU1 Free run Controlled by CPU_STP# Free run Controllable RW
1
0 CPU0 Free run Controlled by CPU_STP# Free run Controllable RW
1
BYTE 10
BYTE 12 - BYTE COUNT - DEFAULT 0x13H
Bit Output(s) affected Description/ Function 0 1 Type Power On
7CFG1 R
See CFG
table 1, 2
6CFG0 R
See CFG
table 1, 2
5 25MHz-EN
25MHz disabled in PD/
M1 (for both PLL3 and PLL2 25MHZ) disabled
Enabled (Can not be reset
by PD restore at power down) RW 0
4Reserved RW
1
3 CPU_ITP_AMT EN
M1 mode CLK enable at M1 mode
Only if ITP_EN = 1 disable enable RW 0
2 CPU1_AMT_EN M1 mode CLK enable at M1 mode disable enable RW 1
1 PCI GEN II GEN II compliance None GEN II GEN II R
1
0
CPU_ITP_STOP
EN Free run control Free run Controlled RW 1
