IDTCV183-2APAG8 Datasheet IDTCV183-2APAG, IDTCV183-2APAG8 | P7-P9

COMMERCIAL TEMPERATURE RANGE

IDTCV183-2A

PROGRAMMABLE FLEXPC CLOCK FOR P4 PROCESSOR

CFB TABLE (PIN 17-18)

ID3,ID2,ID1,ID0 Comments

0000 CK505 56 pin TSSOP CK505 YC

0001 CK505 64 pin TSSOP CK505 YC

0010 48 pin QFN CK505 YC

0011 56 pin QFN CK505 YC

0100 64 pin QFN CK505 YC

0101 72 pin QFN CK505 YC

0110 48 pin SSOP CK505 YC

0111 56 pin SSOP CK505 YC

1000 Reserved CK505 Derivative (non YC)

1001 Reserved

1010 Reserved

1011 Reserved

1100 Reserved

1101 Reserved

1110 Reserved

1111 Reserved

DEVICE ID TABLE

000 0.3V

001 0.4V

010 0.5V

011 0.6V

100 0.7V

101 0.8V

110 0.9V

111 1V

IO_VOUT [2:0] TABLE

CFB[3,2,1,0]

B1b[4:1]

Pin17, 18

0000 SRC (PLL4)

0001 SRC (PLL4)

0010 100MHz 0.5% SSC (PLL3)

0011 100MHz 1.0% SSC (PLL3)

0100 100MHz 1.5% SSC (PLL3)

0101 100MHz 2.0% SSC (PLL3)

110 100MHz 2.5% SSC (PLL3)

0111 Reserved

1000 1394A 3.3V, SSC off Byte4 bit0 lose control

1001 1394A&B 3.3V, SSC off Byte4 bit0 lose control

1010 1394B 3.3V, SSC off Byte4 bit0 lose control

1011

27MHz, 3.3V, Byte4 bit0 control the SSC enable, Byte1 bit5

control the down/center

1100 25MHz 3.3V, SSC off Byte4 bit0 lose control

1101

Pin17 = 25MHz, PLL2

Pin18 = 1394A, PLL3

Both no SSC

1110 Reserved

1111 Reserved

SATA/PCI from PLL3 or PLL4 (see CFG table)

Comments

From PLL3, pin17 = 1394A, pin18 = 1394B, SATA/PCI

from PLL4

default, SATA/PCI from PLL3 or PLL4 (see CFG table)

From PLL3 , SATA/PCI from PLL4

Reserved

From PLL3 , SATA/PCI from PLL4

25MHz from PLL2

1394 from PLL3, SATA/PCI from PLL4

From PLL3 , SATA/PCI from PLL4

COMMERCIAL TEMPERATURE RANGE

IDTCV183-2A

PROGRAMMABLE FLEXPC CLOCK FOR P4 PROCESSOR

BYTE 2

Bit Output(s) Affected Description/Function 0 1 Type Power On

7 REF Output Enable Tristate Enable RW 1

6 USB_48 Output Enable Tristate Enable RW 1

5 PCIF5 Output Enable Tristate Enable RW 1

4 PCI4 Output Enable Tristate Enable RW 1

3 PCI3 Output Enable Tristate Enable RW 1

2 PCI2 Output Enable Tristate Enable RW 1

1 PCI1 Output Enable Tristate Enable RW 1

0 PCI0 Output Enable Tristate Enable RW 1

CONTROL REGISTERS

BYTE 0

NOTES:

1. Sticky 1, can only be reset by power off.

BYTE 1

•

Byte 16 bit 3 has to be "1". This bit will decode the power on latched

value of pins 4, 5 (see CFG table 1).

N-PROGRAMMING PROCEDURE

•

User writes the desired CPU frequency in HEX form into CPUN [8:0],

Byte 16, 17.

•

User writes the desired SRC frequency in HEX form into PN [7:0], Byte

18.

Bit Output(s) Affected Description/Function 0 1 Type Power On

7 FSC Latched FSC R Latched Value

6 FSB Latched FSB R Latched Value

5 FSA Latched FSA R Latched Value

4 iAMT_EN iAMT Mode Legacy Mode Enabled RW HW M1 setting(1)

3Reserved RW 0

2 CFB table enable Enable CFB table

Disable CFB table

(pin 17, 18 is SRC)

RW 0

1 SATA source

Normal, depend on

CFB and CGF table

PLL2 RW 0

0PD_Restore

SMBUS control registers

setting

after the power down

Power on default, With

some exceptions

Save register

contents

RW 1

Bit Output(s) Affected Description/Function 0 1 Type Power On

7 SRC0_sel Pin13/14 mode select SRC0 DOT96 RW 0

6 PLL1_SSC_DC SSC mode selection Down spread Center spread RW 0

5 PLL3_SSC_DC SSC mode selection Down spread Center spread RW 0

4 PLL3_CFB3 RW 0

3 PLL3_CFB2 Only valid if Byte0 bit2 = 0 RW 0

2 PLL3_CFB1 See PLL3_CFB table, RW 0

1 PLL3_CFB0 configure pin17, 18 output mode RW 1

0 PCI Reflect PCI PLL status PLL3 PLL4 R

COMMERCIAL TEMPERATURE RANGE

IDTCV183-2A

PROGRAMMABLE FLEXPC CLOCK FOR P4 PROCESSOR

Bit Output(s) Affected Description/Function 0 1 Type Power On

7 SRC11 Output Enable Tristate Enabled RW 1

6 SRC10 Output Enable Tristate Enabled RW 1

5 SRC9 Output Enable Tristate Enabled RW 1

4 SRC8/ITP Output Enable Tristate Enabled RW 1

3 SRC7 Output Enable Tristate Enabled RW 1

2 SRC6 Output Enable Tristate Enabled RW 1

1 SRC5 Output Enable Tristate Enabled RW 1

0 SRC4 Output Enable Tristate Enabled RW 1

BYTE 3

BYTE 4

Bit Output(s) Affected Description/Function 0 1 Type Power On

7 SRC3 Output Enable Disabled Enabled RW 1

6 SATA/SRC2 Output Enable Disabled Enabled RW 1

5 SRC1 Output Enable Disabled Enabled RW 1

4 SRC0/DOT96 Output Enable Disabled Enabled RW 1

3 CPU1 Output Enable Disabled Enabled RW 1

2 CPU0 Output Enable Disabled Enabled RW 1

1 PLL1_SSC_ON SSC Enable Disabled Enabled RW 1

0 PLL3_SSC_ON SSC Enable Disabled Enabled RW 1

BYTE 5

Bit Output(s) Affected Description/Function 0 1 Type Power On

7 CR#_A Pin1 mode selection PCI0 mode CR#_A mode RW 0

6 CR#_A control CR#_A control selection SRC0 SRC2 RW 0

5 CR#_B Pin3 mode selection PCI1mode CR#_B mode RW 0

4 CR#_B control CR#_B control selection SRC1

(1)

SRC4 RW 0

3 CR#_C Pin24 mode selection SRCT3 mode CR#_C mode RW 0

2 CR#_C control CR#_C control selection SRC0 SRC2 RW 0

1 CR#_D Pin25 mode selection SRCC3 mode CR#_D mode RW 0

0 CR#_D control CR#_D control selection SRC1 SRC4 RW 0

NOTE:

1. Only when SRC1 is SRC Clock.

P1-P3 P4-P6 P7-P9 P10-P12 P13-P15 P16-P18 P19-P21 P22-P22

IDTCV183-2APAG8

Mfr. #:

Buy IDTCV183-2APAG8

Manufacturer:

Description:

IC PROC BRIDGE PCI-HOST 64TSSOP

Lifecycle:

New from this manufacturer.

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IDTCV183-2APAG8

IDTCV183-2APAG8

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