AD9433
Rev. A | Page 18 of 20
01977-045
ANALOG INPUT
The analog input to the AD9433 is a differential buffer. The
input buffer is self-biased by an on-chip resistor divider that
sets the dc common-mode voltage to a nominal 4 V (see the
Equivalent Circuits section). Rated performance is achieved
by driving the input differentially. The minimum input offset
voltage is obtained when driving from a source with a low
differential source impedance, such as a transformer in ac
applications (see Figure 45). Capacitive coupling at the inputs
increases the input offset voltage by as much as 50 mV.
AIN
AD9433
AIN
0.1µF
25Ω
50Ω
1:1
25Ω
NALOG
SIGNAL
SOURCE
Figure 45. Transformer-Coupled Analog Input Circuit
In the highest frequency applications, two transformers con-
nected in series may be necessary to minimize even-order
harmonic distortion. The first transformer isolates and converts
the signal to a differential signal, but the grounded input on the
primary side degrades amplitude balance on the secondary
winding. Capacitive coupling between the windings causes
this imbalance. Because one input to the first transformer is
grounded, there is little or no capacitive coupling, resulting in
an amplitude mismatch at the output of the first transformer. A
second transformer improves the amplitude balance, and thus
improves the harmonic distortion. A wideband transformer,
such as the ADT1-1WT from Mini-Circuits®, is recommended
for these applications, because the bandwidth through the two
transformers is reduced by √2.
01977-046
AIN
AD9433
AIN
0.1µF
25Ω
50Ω
ANALOG
SIGNAL
1:11:1
25Ω
SOURCE
Figure 46. Driving the Analog Input with Two Transformers for Improved
Even-Order Harmonics
Driving the ADC single-ended degrades performance, partic-
ularly even-order harmonics. For best dynamic performance,
impedances at AIN and
AIN
should match. Special care was
taken in the design of the analog input section of the AD9433
to prevent damage and corruption of data when the input is
overdriven.
SFDR OPTIMIZATION
When set to Logic 1, the SFDR MODE pin enables a proprietary
circuit that can improve the spurious-free dynamic range (SFDR)
performance of the AD9433. This pin is useful in applications
where the dynamic range of the system is limited by discrete
Enabling this circuit gives the circuit a dynamic transfer functi
meaning that the voltage t
spurious frequency content caused by nonlinearities in the
ADC transfer function.
on,
hreshold between two adjacent output
er consumption. The output data
V)
codes can change from clock cycle to clock cycle. While improving
spurious frequency content, this dynamic aspect of the transfer
function may be inappropriate for some time domain applications
of the converter. Connecting the SFDR MODE pin to ground
disables this function. The improvement in the linearity of the
converter and its effect on spurious free dynamic range is shown
in Figure 4 and Figure 5 and in Figure 22 and Figure 23.
DIGITAL OUTPUTS
The digital outputs are 3 V (2.7 V to 3.3 V) TTL-/CMOS-
compatible for lower pow
format is selectable through the data format select (DFS)
CMOS input. DFS = 1 selects offset binary; DFS = 0 selects
twos complement coding (see Table 8 and Table 9).
Table 8. Offset Binary Output Coding (DFS = 1, V
REF
= 2.5
Code
AIN −
AIN
(V)
Digital Output
4095 +1.000 1111 1111 1111
… … …
2048 0 1000 0000 0000
2047 0049 1 1111 1111 −0.0 011
… … …
0 −1.000 0000 0000 0000
Table 9. Twos Comple nt Output C
FS = 0, V
REF
=
me
2.5 V)
oding
(D
Code AIN −
AIN
(V) Digital Output
+2047 +1.000 0111 1111 1111
… … …
0 0 0000 0000 0000
−1 −0.00049 1 1111 1111 111
… … …
−2048 −1.000 1000 0000 0000
VOLTAGE RE ENCE
and acc V voltage refer he
mal operation, the internal refer-
hed data outputs, with 10 pipeline
a outputs are available one propagation delay (t
PD
)
he
FER
A stable urate 2.5 ence is built into t
AD9433 (VREFOUT). In nor
ence is used by strapping Pin 45 to Pin 46 and placing a 0.1 µF
decoupling capacitor at VREFIN. The input range can be adjusted
by varying the reference voltage applied to the AD9433. No appre-
ciable degradation in performance occurs when the reference is
adjusted ±5%. The full-scale range of the ADC tracks reference
voltage changes linearly.
TIMING
The AD9433 provides latc
delays. Dat
after the rising edge of the encode command (see Figure 2). T
length of the output data lines and the loads placed on them
should be minimized to reduce transients within the AD9433;
these transients can detract from the dynamic performance of
the converter. The minimum guaranteed conversion rate of the
AD9433 is 10 MSPS. At internal clock rates below 10 MSPS,
dynamic performance may degrade.
