TC520A
DS21431C-page 6 2001-2012 Microchip Technology Inc.
3.0 DETAILED DESCRIPTION
3.1 TC520A Timing
The TC520A consists of a serial port and state
machine. The state machine provides control timing to
the TC5xx A/D converter connected to the TC520A as
well as providing sequential timing for TC520A internal
operation. All timing is derived from the frequency
source at OSC
IN
and OSC
OUT
. This frequency source
can be either an externally provided clock signal or
external crystal. If an external clock is used, it must be
connected to the OSC
IN
pin and OSC
OUT
must remain
floating. If a crystal is used, it must be connected
between the OSC
IN
and OSC
OUT
and be physically
located as close to the OSC
IN
and OSC
OUT
pins as
possible. The incoming frequency is internally divided
by 4 and the resulting clock (SYSCLK) controls all
timing functions.
3.2 TC5XX A/D Converter Control
Signals
The TC520A control outputs (A, B) and control input
(CMPTR) connect directly to the corresponding pins of
the TC5XX A/D converter. A conversion is consum-
mated when A, B have been sequenced through the
required 4 phases of conversion: Auto Zero (AZ), Inte-
grate (INT), De-integrate (D
INT
) and Integrator Zero (IZ)
(see Figure 4-1). The Auto Zero phase compensates
for offset errors in the TC5XX A/D converter. The
Integrate phase connects the voltage to be converted
to the TC5XX A/D converter input, resulting in an inte-
grator output dv/dt directly proportional to the magni-
tude of the applied input voltage. Actual A/D conversion
(counting) is initiated at the start of the DINT phase and
terminates when the integrator output crosses 0V. The
integrator output is then forced to 0V during the IZ
phase and the converter is ready for another cycle.
Please see the TC500/TC500A/TC510/TC514 data
sheet for a complete description of these phases.
The number of SYSCLK periods (counts) for the AZ
and INT phases is determined by the LOAD VALUE.
The LOAD VALUE is a single byte that must be loaded
into the most significant byte of 16-bit counter on board
the TC520A during initialization. The lower byte of this
counter is pre-loaded to a value of 0FFH (256
10
) and
cannot be changed.
The LOAD VALUE (upper 8 bits of the counter) can be
programmed over a range of 0FFH to 00H (corre-
sponding to a range of AZ = INT = 256 counts to 65536
counts). (See Figure 3-2). The LOAD VALUE sets the
number of counts for both the AZ and INT phases and
directly affects resolution and speed of conversion. The
greater the number of counts allowed for AZ and INT,
the greater the A/D resolution (but the slower the con-
version speed).
The time period required for the DINT phase is a func-
tion of the amount of voltage stored on the integrator
during the INT phase and the value of V
REF
. The DINT
phase is initiated by the TC520A immediately after the
INT phase and terminated when the TC5XX A/D con-
verter changes the state of the CMPTR input of the
TC520A, indicating a zero crossing. In general, the
maximum number of counts chosen for DINT is twice
that of INT (with V
REF
chosen at V
ININ(MAX)
/2). Choos-
ing these values guarantees a full count (maximum res-
olution) during D
INT
when V
IN
= V
IN(MAX)
.
The IZ phase is initiated immediately following the D
INT
phase and is maintained until the CMPTR input transi-
tions high. This indicates the integrator is initialized and
ready for another conversion cycle. This phase
typically takes 2msec.
3.3 Serial Port Control Signals
Communication to and from the TC520A is accom-
plished over a 3 wire serial port. Data is clocked into
D
IN
on the rising edge of D
CLK
and clocked out of D
OUT
on the falling edge of D
CLK
. READ must be low to read
from the serial port and can be taken high at any time,
which terminates the read cycle and releases D
OUT
to
a high impedance state. Conversion data is shifted to
the processor from D
OUT
in the following order:
OVERRANGE (which can also be used as the 17th
data bit), POLARITY, conversion data (MSB first).
