LTC6362
5
6362fa
ELECTRICAL CHARACTERISTICS
The l denotes the specifications which apply over the full operating
temperature range, otherwise specifications are at T
A
= 25°C. V
+
= 5V, V
–
= 0V, V
CM
= V
OCM
= V
ICM
= 2.5V, V
SHDN
= open. V
S
is defined
as (V
+
– V
–
). V
OUTCM
is defined as (V
+OUT
+ V
–OUT
)/2. V
ICM
is defined as (V
+IN
+ V
–IN
)/2. V
OUTDIFF
is defined as (V
+OUT
– V
–OUT
).
Note 1: Stresses beyond those listed under Absolute Maximum Ratings
may cause permanent damage to the device. Exposure to any Absolute
Maximum Rating condition for extended periods may affect device
reliability and lifetime.
Note 2: Input pins (+IN, –IN, V
OCM
and SHDN) are protected by steering
diodes to either supply. If the inputs should exceed either supply voltage,
the input current should be limited to less than 10mA. In addition, the
inputs +IN, –IN are protected by a pair of back-to-back diodes. If the
differential input voltage exceeds 1.4V, the input current should be limited
to less than 10mA.
Note 3: A heat sink may be required to keep the junction temperature
below the absolute maximum rating when the output is shorted
indefinitely.
Note 4: The LTC6362C and LTC6362I are guaranteed functional over
the operating temperature range of –40°C to 85°C. The LTC6362H is
guaranteed functional over the operating temperature range of –40°C to
125°C.
Note 5: The LTC6362C is guaranteed to meet specified performance from
0°C to 70°C.The LTC6362I is guaranteed to meet specified performance
from –40°C to 85°C. The LTC6362C is designed, characterized and
expected to meet specified performance from –40°C to 85°C, but is not
tested or QA sampled at these temperatures. The LTC6362H is guaranteed
to meet specified performance from –40°C to 125°C.
Note 6: Differential input referred offset voltage includes offset due to
input offset current across 1k source resistance.
Note 7: Maximum differential input referred offset voltage drift is
determined by a large sampling of typical parts. Drift is not guaranteed by
test or QA sampled at this value.
Note 8: Input bias current is defined as the maximum of the input currents
flowing into either of the input pins (–IN and +IN). Input Offset current is
defined as the difference between the input currents (I
OS
= I
B
+
– I
B
–
).
Note 9: Input common mode range is tested by verifying that at the limits
stated in the Electrical Characteristics table, the differential offset (V
OSDIFF
)
and common mode offset (V
OSCM
) have not deviated by more than ±1mV
and ±35mV respectively compared to the V
ICM
= 2.5V (at V
S
= 5V) and
V
ICM
= 1.5V (at V
S
= 3V) cases.
Output common mode range is tested by verifying that at the limits stated
in the Electrical Characteristics table, the common mode offset (V
OSCM
)
has not deviated by more than ±15mV compared to the V
OCM
= 2.5V
(at V
S
= 5V) and V
OCM
= 1.5V (at V
S
= 3V) cases.
Note 10: Input CMRR is defined as the ratio of the change in the input
common mode voltage at the pins +IN or –IN to the change in differential
input referred offset voltage. Output CMRR is defined as the ratio of
the change in the voltage at the V
OCM
pin to the change in differential
input referred offset voltage. This specification is strongly dependent on
feedback ratio matching between the two outputs and their respective
inputs and it is difficult to measure actual amplifier performance (see
Effects of Resistor Pair Mismatch in the Applications Information section
of this data sheet). For a better indicator of actual amplifier performance
independent of feedback component matching, refer to the PSRR
specification.
Note 11: Differential power supply rejection (PSRR) is defined as the
ratio of the change in supply voltage to the change in differential input
referred offset voltage. Common mode power supply rejection (PSRRCM)
is defined as the ratio of the change in supply voltage to the change in the
common mode offset voltage.
Note 12: Supply voltage range is guaranteed by power supply rejection
ratio test.
SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS
V
IL
SHDN Input Logic Low
l
0.8 V
V
IH
SHDN Input Logic High
l
2 V
t
ON
Turn-On Time 2 μs
t
OFF
Turn-Off Time 2 μs
