MAX9248/MAX9250
27-Bit, 2.5MHz to 42MHz
DC-Balanced LVDS Deserializers
______________________________________________________________________________________ 15
Input Frequency Detection
A frequency-detection circuit detects when the LVDS
input is not switching. When not switching, all outputs
except LOCK are low, LOCK is high, and PCLK_OUT
follows REFCLK. This condition occurs, for example, if
the serializer is not driving the interconnect or if the
interconnect is open.
Frequency Range Setting (RNG[1:0])
The RNG[1:0] inputs select the operating frequency
range of the MAX9248/MAX9250 and the transition time
of the outputs. Select the frequency range that includes
the MAX9247 serializer PCLK_IN frequency. Table 3
shows the selectable frequency ranges and the corre-
sponding data rates and output transition times.
Power Down
Driving PWRDWN low puts the outputs in high imped-
ance and stops the PLL. With PWRDWN ≤ 0.3V and all
LVTTL/LVCMOS inputs ≤ 0.3V or ≥ V
CC
- 0.3V, the sup-
ply current is reduced to less than 50µA. Driving
PWRDWN high initiates lock to the local reference clock
(REFCLK) and afterwards to the serial input.
Lock and Loss-of-Lock (
LOCK
)
When PWRDWN is driven high, the PLL begins locking
to REFCLK, drives LOCK from high impedance to high
and the other outputs from high impedance to low,
except PCLK_OUT. PCLK_OUT outputs REFCLK while
the PLL is locking to REFCLK. Lock to REFCLK takes a
maximum of 16,928 REFCLK cycles for the MAX9250.
The MAX9248 has an additional spread-spectrum PLL
(SSPLL) that also begins locking to REFCLK. Locking
both PLLs to REFCLK takes a maximum of 33,600 REFCLK
cycles for the MAX9248.
When the MAX9248/MAX9250 complete their lock to
REFCLK, the serial input is monitored for a transition
word. When a transition word is found, LOCK output is
driven low, indicating valid output data and the parallel
rate clock recovered from the serial input is output on
PCLK_OUT. The MAX9248 SSPLL waits an additional
288 clock cycles after the transition word is found
before LOCK is driven low and sequence takes effect.
PCLK_OUT is stretched on the change from REFCLK to
recovered clock (or vice versa) at the time when the
transition word is found.
If a transition word is not detected within 2
22
cycles of
PCLK_OUT, LOCK is driven high, the other outputs
except PCLK_OUT are driven low. REFCLK is output on
PCLK_OUT and the deserializer continues monitoring
the serial input for a transition word. See Figure 7 for
the MAX9250 and Figure 8 for the MAX9248 regarding
the synchronization timing diagram.
The MAX9248 input-to-output delay can be as low as
(4.5t
T
+ 8.0)ns or as high as (36t
T
+ 16)ns due to
spread-spectrum variations (see Figure 6).
The MAX9250 input-to-output delay can be as low as
(3.575t
T
+ 8)ns or as high as (3.725t
T
+ 16)ns.
