MAX9248/MAX9250
27-Bit, 2.5MHz to 42MHz
DC-Balanced LVDS Deserializers
4 _______________________________________________________________________________________
AC ELECTRICAL CHARACTERISTICS
(V
CC_
= +3.0V to +3.6V, C
L
= 8pF, PWRDWN = high, differential input voltage ⏐V
ID
⏐ = 0.1V to 1.2V, input common-mode voltage
V
CM
= ⏐V
ID
/ 2⏐ to V
CC
- ⏐V
ID
/ 2⏐, T
A
= -40°C to +105°C, unless otherwise noted. Typical values are at V
CC_
= +3.3V, ⏐V
ID
⏐ = 0.2V,
V
CM
= 1.2V, T
A
= +25°C.) (Notes 3, 5)
PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS
REFCLK TIMING REQUIREMENTS
MAX9248/MAX9250ECM 23.8 400.0
Period t
T
MAX9248/MAX9250GCM 28.6 400.0
ns
MAX9248/MAX9250ECM 2.5 42.0
Frequency f
CLK
MAX9248/MAX9250GCM 2.5 35.0
MHz
Frequency Variation Δf
CLK
REFCLK to serializer PCLK_IN -2.0 +2.0 %
Duty Cycle DC 40 50 60 %
Transition Time t
TRAN
20% to 80% 6 ns
SWITCHING CHARACTERISTICS
MAX9248/
MAX9250ECM
2.2 4.6
RNG1 = high
MAX9248/
MAX9250GCM
2.2 4.9
MAX9248/
MAX9250ECM
2.8 5.2
Output Rise Time t
R
Figure 3
RNG1 = low
MAX9248/
MAX9250GCM
2.8 6.1
ns
RNG1 = high
MAX9248/
MAX9250ECM
1.9 4.0
MAX9248/
MAX9250ECM
2.3 4.3
Output Fall Time t
R
Figure 3
RNG1 = low
MAX9248/
MAX9250GCM
2.3 5.2
ns
PCLK_OUT High Time t
HIGH
Figure 4
0.4 x
t
T
0.45 x
t
T
0.6 x
t
T
ns
PCLK_OUT Low Time t
LOW
Figure 4
0.4 x
t
T
0.45 x
t
T
0.6 x
t
T
ns
Data Valid Before PCLK_OUT t
DVB
Figure 5 0.35 x t
T
0.4 x t
T
ns
Data Valid After PCLK_OUT t
DVA
Figure 5 0.35 x t
T
0.4 x t
T
ns
MAX9248, Figure 8 33,600 x t
T
PLL Lock to REFCLK t
PLLREF
MAX9250, Figure 7 16,928 x t
T
ns
Maximum output
frequency
f
REFCLK
+ 3.6%
f
REFCLK
+ 4.0%
f
REFCLK
+ 4.4%
SS = high,
Figure 11
Minimum output
frequency
f
REFCLK
- 4.4%
f
REFCLK
- 4.0%
f
REFCLK
- 3.6%
Maximum output
frequency
f
REFCLK
+ 1.8%
f
REFCLK
+ 2.0%
f
REFCLK
+ 2.2%
Spread-Spectrum Output
Frequency (MAX9248)
f
PCLK_OUT
SS = low,
Figure 11
Minimum output
frequency
f
REFCLK
- 2.2%
f
REFCLK
- 2.0%
f
REFCLK
- 1.8%
MHz
