© 2007 Microchip Technology Inc. DS21293C-page 17
MCP3001
6.2 Maintaining Minimum Clock Speed
When the MCP3001 initiates the sample period, charge
is stored on the sample capacitor. When the sample
period is complete, the device converts one bit for each
clock that is received. It is important for the user to note
that a slow clock rate will allow charge to bleed off the
sample cap while the conversion is taking place. At
85°C (worst case condition), the part will maintain
proper charge on the sample cap for 700 µs at
V
DD
= 2.7V and 1.5 ms at V
DD
= 5V. This means that at
V
DD
= 2.7V, the time it takes to transmit the first 14
clocks must not exceed 700 µs. Failure to meet this cri-
terion may induce linearity errors into the conversion
outside the rated specifications.
6.3 Buffering/Filtering the Analog Inputs
If the signal source for the ADC is not a low impedance
source, it will have to be buffered or inaccurate conver-
sion results may occur. See Figure 4-2. It is also rec-
ommended that a filter be used to eliminate any signals
that may be aliased back into the conversion results.
This is illustrated in Figure 6-3 where an op amp is
used to drive, filter and gain the analog input of the
MCP3001. This amplifier provides a low impedance
source for the converter input and a low pass filter,
which eliminates unwanted high frequency noise.
Low pass (anti-aliasing) filters can be designed using
Microchip’s interactive FilterLab™ software. FilterLab
will calculate capacitor and resistor values, as well as
determine the number of poles that are required for the
application. For more information on filtering signals,
see the application note AN699 “Anti-Aliasing Analog
Filters for Data Acquisition Systems.”
FIGURE 6-3: The MCP601 operational amplifier is
used to implement a 2nd order anti-aliasing filter for
the signal being converted by the MCP3001.
6.4 Layout Considerations
When laying out a printed circuit board for use with
analog components, care should be taken to reduce
noise wherever possible. A bypass capacitor should
always be used with this device and should be placed
as close as possible to the device pin. A bypass capac-
itor value of 1 µF is recommended.
Digital and analog traces should be separated as much
as possible on the board and no traces should run
underneath the device or the bypass capacitor. Extra
precautions should be taken to keep traces with high
frequency signals (such as clock lines) as far as possi-
ble from analog traces.
Use of an analog ground plane is recommended in
order to keep the ground potential the same for all
devices on the board. Providing V
DD
connections to
devices in a “star” configuration can also reduce noise
by eliminating current return paths and associated
errors. See Figure 6-4. For more information on layout
tips when using ADC, refer to AN-688 “Layout Tips for
12-Bit A/D Converter Applications”.
FIGURE 6-4: V
DD
traces arranged in a ‘Star’
configuration in order to reduce errors caused by
current return paths.
MCP3001
V
DD
10 µF
IN-
IN+
-
+
V
IN
C
1
C
2
V
REF
4.096V
Reference
1µF
10 µF
0.1 µF
MCP601
R
1
R
2
R
3
R
4
MCP1541
C
L
V
DD
Connection
Device 1
Device 2
Device 3
Device 4
