70V3389S5BC8 Datasheet 70V3389S6BC, 70V3389S4BCG, 70V3389S5BFI8 | P1-P3

OCTOBER 2014

DSC 4832/13

1



CNTRST

R

Counter/

Address

Reg.

A

15R

A

0R

Counter/

Address

Reg.

CNTEN

R

ADS

R

CNTEN

L

ADS

L

CNTRST

L

Dout0-8_L

Dout9-17_L

Dout0-8_R

Dout9-17_R

B

W

0

L

B

W

1

L

B

W

1

R

B

W

0

R

I/O

0L

-I/O

17L

I/O

0R

-I/O

17R

Din_L

ADDR_L

Din_R

ADDR_R

OE

R

OE

L

4832 tbl 01

UB

L

LB

L

R/W

L

CE

0L

UB

R

LB

R

R/W

R

CE

0R

CE

1R

CE

1L

64K x 18

MEMORY

ARRAY

CLK

R

CLK

L

.

A

15L

A

0L

Functional Block Diagram

Features

◆

True Dual-Port memory cells which allow simultaneous

access of the same memory location

◆

High-speed clock to data access

– Commercial: 4.2/5/6ns (max.)

– Industrial: 5ns (max)

◆

Pipelined output mode

◆

Counter enable and reset features

◆

Dual chip enables allow for depth expansion without

additional logic

◆

Full synchronous operation on both ports

– 7.5ns cycle time, 133MHz operation (9.6 Gbps bandwidth)

– Fast 4.2ns clock to data out

– 1.8ns setup to clock and 0.7ns hold on all control, data, and

address inputs @ 133MHz

– Data input, address, byte enable and control registers

– Self-timed write allows fast cycle time

◆

Separate byte controls for multiplexed bus and bus

matching compatibility

◆

LVTTL- compatible, single 3.3V (±150mV) power supply for

core

◆

LVTTL- compatible, selectable 3.3V (±150mV)/2.5V (±125mV)

power supply for I/Os and control signals on each port

◆

Industrial temperature range (-40°C to +85°C) is

available for selected speeds

◆

Available in a 128-pin Thin Quad Plastic Flatpack (TQFP),

208-pin fine pitch Ball Grid Array, and 256-pin Ball

Grid Array

IDT70V3389S

HIGH-SPEED 3.3V 64K x 18

SYNCHRONOUS PIPELINED

DUAL-PORT STATIC RAM

WITH 3.3V OR 2.5V INTERFACE

◆

Green parts available, see ordering information

6.42

IDT70V3389S

High-Speed 64K x 18 3.3V Dual-Port Synchronous Pipelined Static RAM Industrial and Commercial Temperature Ranges

2

Description:

The IDT70V3389 is a high-speed 64K x 18 bit synchronous Dual-Port

RAM. The memory array utilizes Dual-Port memory cells to allow

simultaneous access of any address from both ports. Registers on control,

data, and address inputs provide minimal setup and hold times. The timing

latitude provided by this approach allows systems to be designed with very

short cycle times. With an input data register, the IDT70V3389 has been

optimized for applications having unidirectional or bidirectional data flow

in bursts. An automatic power down feature, controlled by CE0 and

CE

1, permits the on-chip circuitry of each port to enter a very low

standby power mode.

The 70V3389 can support an operating voltage of either 3.3V or

2.5V on one or both ports, controllable by the OPT pins. The power

supply for the core of the device (V

DD) remains at 3.3V.

Pin Configuration

(1,2,3,4)

NOTES:

1. All V

DD pins must be connected to 3.3V power supply.

2. All V

DDQ pins must be connected to appropriate power supply: 3.3V if OPT pin for that port is set to VIH (3.3V), and 2.5V if OPT pin for that port is

set to V

IL (0V).

3. All V

SS pins must be connected to ground supply.

4. Package body is approximately 15mm x 15mm x 1.4mm with 0.8mm ball pitch.

5. This package code is used to reference the package diagram.

6. This text does not indicate orientation of the actual part-marking.

1716

15

1412 13

10

9876543

21

11

A

B

C

D

E

F

G

H

J

K

L

M

N

P

R

T

U

I/O

9L

NC V

SS

NC

A

2L

A

4L

CLK

L

A

8L

A

12L

NC

NC OPT

L

NC

V

SS

NC

V

SS

A

1L

A

5L

A

9L

A

13L

NC

V

DDQL

I/O

9R

V

DDQR

V

DD

A

3L

A

6L

NC

A

10L

A

14L

NC

NC V

SS

I/O

10L

NC

I/O

11L

NC

V

DDQR

I/O

10R

NC

I/O

11R

NC

V

SS

V

DD

NC I/O

12L

V

DD

V

SS

V

SS

NC

V

SS

I/O

12R

CNTRST

R

NC I/O

14L

V

DDQR

V

DDQL

I/O

15R

NC

V

SS

NCNC

A

15L

A

11L

A

7L

A

0L

NC

I/O

7L

NC

I/O

6L

I/O

8R

UB

L

NC

I/O

8L

V

DDQL

CE

0L

CE

1L

LB

L

CN TRST

L

OE

L

I/O

0L

I/O

2L

I/O

1R

ADS

R

R/W

R

NC

I/O

16R

I/O

15L

NC

A

13R

A

12R

NC

V

DD

CLK

R

I/O

0R

NC

V

SS

A

5R

A

9R

CE

0R

CE

1R

V

DD

V

SS

NC

A

14R

A

10R

UB

R

V

SS

V

DDQL

I/O

1L

I/O

2R

NC

NC A

15R

A

11R

A

7R

LB

R

OE

R

V

SS

NC

V

DDQL

OPT

R

NC

70V3389BF

BF-208

(5)

208-Pin fpBGA

Top View

(6)

4832 tbl 02

I/O

14R

V

DDQL

V

SS

V

DDQR

NC

I/O

7R

NC

R/W

L

NC

ADS

L

V

DDQL

I/O

13R

CNTEN

L

V

SS

I/O

13L

V

SS

I/O

16L

V

DDQR

V

SS

I/O

17R

I/O

17L

V

DDQL

V

SS

V

DD

A

8R

CNTEN

R

A

6R

A

3R

A

1R

A

2R

A

0R

I/O

3L

I/O

4L

A

4R

V

DD

V

SS

V

SS

V

SS

V

DDQR

V

DDQL

V

SS

V

DDQR

V

SS

I/O

3R

I/O

4R

V

SS

V

DDQR

V

SS

V

DD

V

SS

V

DD

V

SS

I/O

5R

I/O

5L

V

DDQR

I/O

6R

V

SS

V

SS

V

DDQL

V

DD

V

SS

V

DDQR

V

SS

V

SS

V

DD

V

DD

V

SS

V

DD

V

SS

12/12/01

6.42

IDT70V3389S

High-Speed 64K x 18 3.3V Dual-Port Synchronous Pipelined Static RAM Industrial and Commercial Temperature Ranges

3

Pin Configuration

(1,2,3,4)

(con't.)

NOTES:

1. All V

DD pins must be connected to 3.3V power supply.

2. All V

DDQ pins must be connected to appropriate power supply: 3.3V if OPT pin for that port is set to VIH (3.3V), and 2.5V if OPT pin for that port is

set to V

IL (0V).

3. All V

SS pins must be connected to ground supply.

4. Package body is approximately 17mm x 17mm x 1.4mm, with 1.0mm ball-pitch.

5. This package code is used to reference the package diagram.

6. This text does not indicate orientation of the actual part-marking.

70V3389BC

BC-256

(5)

256-Pin BGA

Top View

(6)

E16

I/O

7R

D16

I/O

8R

C16

I/O

8L

B16

NC

A16

NC

A15

NC

B15

NC

C15

NC

D15

NC

E15

I/O

7L

E14

NC

D14

NC

D13

V

DD

C12

A

6L

C14

OPT

L

B14

V

DD

A14

A

0L

A12

A

5L

B12

A

4L

C11

ADS

L

D12

V

DDQR

D11

V

DDQR

C10

CLK

L

B11

CNT RST

L

A11

CNTEN

L

D8

V

DDQR

C8

NC

A9

CE

1L

D9

V

DDQL

C9

LB

L

B9

CE

0L

D10

V

DDQL

C7

A

7L

B8

UB

L

A8

NC

B13

A

1L

A13

A

2L

A10

OE

L

D7

V

DDQR

B7

A

9L

A7

A

8L

B6

A

12L

C6

A

10L

D6

V

DDQL

A5

A

14L

B5

A

15L

C5

A

13L

D5

V

DDQL

A4

NC

B4

NC

C4

NC

D4

V

DD

A3

NC

B3

NC

C3

V

SS

D3

NC

D2

I/O

9R

C2

I/O

9L

B2

NC

A2

NC

A1

NC

B1

NC

C1

NC

D1

NC

E1

I/O

10R

E2

I/O

10L

E3

NC

E4

V

DDQL

F1

I/O

11L

F2

NC

F4

V

DDQL

G1

NC

G2

NC

G3

I/O

12L

G4

V

DDQR

H1

NC

H2

I/O

12R

H3

NC

H4

V

DDQR

J1

I/O

13L

J2

I/O

14R

J3

I/O

13R

J4

V

DDQL

K1

NC

K2

NC

K3

I/O

14L

K4

V

DDQL

L1

I/O

15L

L2

NC

L3

I/O

15R

L4

V

DDQR

M1

I/O

16R

M2

I/O

16L

M3

NC

M4

V

DDQR

N1

NC

N2

I/O

17R

N3

NC

N4

V

DD

P1

NC

P2

I/O

17L

P3

NC

P4

NC

R1

NC

R2

NC

R3

NC

R4

NC

T1

NC

T2

NC

T3

NC

T4

NC

P5

A

13R

R5

A

15R

P12

A

6R

P8

NC

P9

LB

R

R8

UB

R

T8

NC

P10

CLK

R

T11

CNTEN

R

P11

ADS

R

R12

A

4R

T12

A

5R

P13

A

3R

P7

A

7R

R13

A

1R

T13

A

2R

R6

A

12R

T5

A

14R

T14

A

0R

R14

OPT

R

P14

NC

P15

NC

R15

NC

T15

NC

T16

NC

R16

NC

P16

I/O

0L

N16

NC

N15

I/O

0R

N14

NC

M16

NC

M15

I/O

1L

M14

I/O

1R

L16

I/O

2R

L15

NC

L14

I/O

2L

K16

I/O

3L

K15

NC

K14

NC

J16

I/O

4L

J15

I/O

3R

J14

I/O

4R

H16

I/O

5R

H15

NC

H14

NC

G16

NC

G15

NC

G14

I/O

5L

F16

I/O

6L

F14

I/O

6R

F15

NC

R9

CE

0R

R11

CNTRST

R

T6

A

11R

T9

CE

1R

A6

A

11L

B10

R/W

L

C13

A

3L

P6

A

10R

R10

R/W

R

R7

A

9R

T10

OE

R

T7

A

8R

,

E5

V

DD

E6

V

DD

E7

V

SS

E8

V

SS

E9

V

SS

E10

V

SS

E11

V

DD

E12

V

DD

E13

V

DDQR

F5

V

DD

F6

V

SS

F8

V

SS

F9

V

SS

F10

V

SS

F12

V

DD

F13

V

DDQR

G5

V

SS

G6

V

SS

G7

V

SS

G8

V

SS

G9

V

SS

G10

V

SS

G11

V

SS

G12

V

SS

G13

V

DDQL

H5

V

SS

H6

V

SS

H7

V

SS

H8

V

SS

H9

V

SS

H10

V

SS

H11

V

SS

H12

V

SS

H13

V

DDQL

J5

V

SS

J6

V

SS

J7

V

SS

J8

V

SS

J9

V

SS

J10

V

SS

J11

V

SS

J12

V

SS

J13

V

DDQR

K5

V

SS

K6

V

SS

K7

V

SS

K8

V

SS

L5

V

DD

L6

V

SS

L7

V

SS

L8

V

SS

M5

V

DD

M6

V

DD

M7

V

SS

M8

V

SS

N5

V

DDQR

N6

V

DDQR

N7

V

DDQL

N8

V

DDQL

K9

V

SS

K10

V

SS

K11

V

SS

K12

V

SS

L9

V

SS

L10

V

SS

L11

V

SS

L12

V

DD

M9

V

SS

M10

V

SS

M11

V

DD

M12

V

DD

N9

V

DDQR

N10

V

DDQR

N11

V

DDQL

N12

V

DDQL

K13

V

DDQR

L13

V

DDQL

M13

V

DDQL

N13

V

DD

F7

V

SS

F11

V

SS

4832 drw 02c

,

F3

I/O

11R

12/12/01

70V3389S5BC8

70V3389S5BC8

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