6.42
IDT70V3389S
High-Speed 64K x 18 3.3V Dual-Port Synchronous Pipelined Static RAM Industrial and Commercial Temperature Ranges
4
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
102
101
100
99
98
97
96
95
94
93
92
90
89
88
87
86
85
84
83
82
81
80
79
78
77
76
75
74
73
72
70
69
68
67
66
65
91
71
A
14L
A
15L
V
SS
NC
IO
9L
IO
9R
V
DDQL
V
SS
IO
10L
IO
10R
V
DDQR
V
SS
IO
11L
IO
11R
IO
12L
IO
12R
V
DD
V
DD
V
SS
V
SS
IO
13R
IO
13L
IO
14R
IO
14L
IO
15R
IO
15L
V
DDQL
V
SS
IO
16R
IO
16L
V
DDQR
V
SS
IO
17R
IO
17L
NC
NC
A
15R
A
14R
A
1R
A
0R
OPT
R
IO
0L
IO
0R
V
DDQR
V
SS
IO
1L
IO
1R
V
DDQL
V
SS
IO
2L
IO
2R
IO
3L
IO
3R
IO
4L
IO
4R
V
SS
V
SS
V
DD
V
DD
IO
5L
IO
5R
V
DDQR
V
SS
IO
7R
IO
7L
V
DDQL
V
SS
NC (V
SS
)
(7)
IO
8R
IO
8L
NC (V
SS
)
(7)
OPT
L
A
0L
A
1L
IO
6R
IO
6L
70V3389PRF
PK-128
(5)
128-Pin TQFP
Top View
(6)
4832 drw 02a
A
1
3
L
A
1
2
L
A
1
1
L
A
1
0
L
A
9
L
A
8
L
A
7
L
U
B
L
L
B
L
C
E
1
L
C
E
0
L
V
D
D
V
D
D
V
S
S
V
S
S
C
L
K
L
O
E
L
R
/
W
L
A
D
S
L
C
N
T
E
N
L
C
N
T
R
S
T
L
A
6
L
A
5
L
A
4
L
A
3
L
A
2
L
A
1
3
R
A
1
2
R
A
1
1
R
A
1
0
R
A
9
R
A
8
R
A
7
R
U
B
R
L
B
R
C
E
1
R
C
E
0
R
V
D
D
V
D
D
V
S
S
V
S
S
C
L
K
R
O
E
R
R
/
W
R
A
D
S
R
C
N
T
E
N
R
C
N
T
R
S
T
R
A
6
R
A
5
R
A
4
R
A
3
R
A
2
R
3
9
4
0
4
1
4
2
4
3
4
4
4
5
4
6
4
7
4
8
4
9
5
0
5
1
5
2
5
3
5
4
5
5
5
6
5
7
5
8
5
9
6
0
6
1
6
2
6
3
6
4
1
2
8
1
2
7
1
2
6
1
2
5
1
2
4
1
2
3
1
2
2
1
2
1
1
2
0
1
1
9
1
1
8
1
1
7
1
1
6
1
1
5
1
1
4
1
1
3
1
1
2
1
1
1
1
1
0
1
0
9
1
0
8
1
0
7
1
0
6
1
0
5
1
0
4
1
0
3
.
12/12/01
Pin Configuration
(1,2,3,4)
(con't.)
NOTES:
1. All V
DD pins must be connected to 3.3V power supply.
2. All V
DDQ pins must be connected to appropriate power supply: 3.3V if OPT pin for that port is set to VIH (3.3V), and 2.5V if OPT pin for that port is
set to V
IL (0V).
3. All V
SS pins must be connected to ground supply.
4. Package body is approximately 14mm x 20mm x 1.4mm.
5. This package code is used to reference the package diagram.
6. This text does not indicate orientation of the actual part-marking.
7. In the 70V3379 (32K x 18) and 70V3389 (64K x 18), pins 96 and 99 are NC. The upgrade devices 70V3399 (128K x 18) and 70V3319 (256K x 18) assign
these pins as V
SS. Customers who plan to take advantage of the upgrade path should treat these pins as VSS on the 70V3379 and 70V3389. If no upgrade is
needed, the pins can be treated as NC.
6.42
IDT70V3389S
High-Speed 64K x 18 3.3V Dual-Port Synchronous Pipelined Static RAM Industrial and Commercial Temperature Ranges
5
NOTES:
1. "H" = V
IH, "L" = VIL, "X" = Don't Care.
2. ADS, CNTEN, CNTRST = X.
3. OE is an asynchronous input signal.
Truth Table I—Read/Write and Enable Control
(1,2,3)
Pin Names
Left Port Right Port Names
CE
0L
,
CE
1L
CE
0R
,
CE
1R
Chip Enables
R/W
L
R/W
R
Read/Write Enable
OE
L
OE
R
Output Enable
A
0L
- A
15L
A
0R
- A
15R
Address
I/O
0L
- I/O
17L
I/O
0R
- I/O
17R
Data Input/Output
CLK
L
CLK
R
Clock
ADS
L
ADS
R
Address Strobe Enable
CNTEN
L
CNTEN
R
Counter Enable
CNTRST
L
CNTRST
R
Counter Reset
UB
L
- LB
L
UB
R
- LB
R
Byte Enables (9-bit bytes)
V
DDQ L
V
DDQR
Power (I/O Bus) (3.3V or 2.5V)
(1)
OPT
L
OPT
R
Option for selecting V
DDQX
(1,2)
V
DD
Power (3.3V)
(1 )
V
SS
Ground (0V)
4832 tbl 01
OE
CLK
CE
0
CE
1
UB LB
R/W
Upper Byte
I/O
9-18
Lower Byte
I/O
0-8
MODE
X
L H H H X High-Z High-Z All Bytes Deselected
X
LHHLLHigh-Z D
IN
Write to Lower Byte Only
X
LHLHL D
IN
High-Z Write to Upper Byte Only
X
LHLLL D
IN
D
IN
Write to Both Bytes
L
LHHLHHigh-ZD
OUT
Read Lower Byte Only
L
LHLHH D
OUT
High-Z Read Upper Byte Only
L
LHLLH D
OUT
D
OUT
Read Both Bytes
H
L H L L X High-Z High-Z Outputs Disabled
4832 tbl 02
NOTES:
1. V
DD, OPTX, and VDDQX must be set to appropriate operating levels prior to
applying inputs on the I/Os and controls for that port.
2. OPT
X selects the operating voltage levels for the I/Os and controls on that port.
If OPT
X is set to VIH (3.3V), then that port's I/Os and controls will operate at 3.3V
levels and V
DDQX must be supplied at 3.3V. If OPTX is set to VIL (0V), then that
port's I/Os and controls will operate at 2.5V levels and V
DDQX must be supplied
at 2.5V. The OPT pins are independent of one another—both ports can operate
at 3.3V levels, both can operate at 2.5V levels, or either can operate at 3.3V
with the other at 2.5V.
6.42
IDT70V3389S
High-Speed 64K x 18 3.3V Dual-Port Synchronous Pipelined Static RAM Industrial and Commercial Temperature Ranges
6
Recommended Operating
Temperature and Supply Voltage
(1)
Absolute Maximum Ratings
(1)
Truth Table II—Address Counter Control
(1,2)
NOTES:
1. "H" = V
IH, "L" = VIL, "X" = Don't Care.
2. Read and write operations are controlled by the appropriate setting of R/W, CE
0, CE1, BEn and OE.
3. Outputs are in Pipelined mode: the data out will be delayed by one cycle.
4. ADS and CNTRST are independent of all other memory control signals including CE
0, CE1 and BEn
5. The address counter advances if CNTEN = V
IL on the rising edge of CLK, regardless of all other memory control signals including CE0, CE1, BEn.
NOTES:
1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may
cause permanent damage to the device. This is a stress rating only and functional
operation of the device at these or any other conditions above those indicated
in the operational sections of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect reliability.
2. V
TERM must not exceed VDD + 150mV for more than 25% of the cycle time or
4ns maximum, and is limited to
< 20mA for the period of VTERM > VDD + 150mV.
NOTES:
1. Industrial temperature: for specific speeds, packages and powers contact your
sales office.
Address
Previous
Address
Addr
Used CLK
ADS CNT EN CNTRS T
I/O
(3)
MODE
XX0
XX L
(4)
D
I/ O
(0) Counter Reset to Address 0
An X An
L
(4 )
XHD
I/O
(n) External Address Used
An Ap Ap
HH H D
I/O
(p) External Address Blocked—Counter disabled (Ap reused)
XApAp + 1
H L
(5)
HD
I/O
(p+1) Counter Enabled—Internal Address generation
4832 tbl 03
Grade
Ambient
Temperature GND V
DD
Commercial 0
O
C to +70
O
C0V3.3V
+
150mV
Industrial -40
O
C to +85
O
C0V3.3V
+
150mV
4832 tbl 04
Symbol Parameter Min. Typ. Max. Unit
V
DD
Core Supply Voltage 3.15 3.3 3.45 V
V
DDQ
I/O Supply Voltage
(3 )
2.375 2.5 2.625 V
V
SS
Ground 0 0 0 V
V
IH
Input High Voltage
(3 )
(Address & Control Inputs)
1.7
____
V
DDQ
+ 125mV
(2 )
V
V
IH
Input High Voltage - I/O
(3 )
1.7
____
V
DDQ
+ 125mV
(2 )
V
V
IL
Input Low Voltage -0.3
(1 )
____
0.7 V
4832 tbl 05a
Symbol Rating Commercial
& Industrial
Unit
V
TE R M
(2 )
Terminal Voltage
with Respect to
GND
-0.5 to +4.6 V
T
BIAS
Temperature
Under Bias
-55 to +125
o
C
T
STG
Storage
Temperature
-65 to +150
o
C
I
OUT
DC Output Current 50 mA
4832 tbl 06
Recommended DC Operating
Conditions with V
DDQ at 2.5V
NOTES:
1. V
IL > -1.5V for pulse width less than 10 ns.
2. V
TERM must not exceed VDDQ + 125mV.
3. To select operation at 2.5V levels on the I/Os and controls of a given port, the
OPT pin for that port must be set to V
IL (0V), and VDDQX for that port must be
supplied as indicated above.
Recommended DC Operating
Conditions with V
DDQ at 3.3V
NOTES:
1. V
IL > -1.5V for pulse width less than 10 ns.
2. V
TERM must not exceed VDDQ + 150mV.
3. To select operation at 3.3V levels on the I/Os and controls of a given port, the
OPT pin for that port must be set to V
IH (3.3V), and VDDQX for that port must be
supplied as indicated above.
Symbol Parameter Min. Typ. Max. Unit
V
DD
Core Supply Voltage 3.15 3.3 3.45 V
V
DDQ
I/O Supply Voltage
(3)
3.15 3.3 3.45 V
V
SS
Ground 0 0 0 V
V
IH
Input High Voltage
(Address & Control Inputs)
(3)
2.0
____
V
DDQ
+ 150mV
(2)
V
V
IH
Input High Voltage - I/O
(3)
2.0
____
V
DDQ
+ 150mV
(2)
V
V
IL
Input Low Voltage -0.3
(1)
____
0.8 V
4832 tbl 05b

70V3389S5BC8

Mfr. #:
Manufacturer:
IDT
Description:
SRAM 64Kx18 STD-PWR 3.3V SYNC DUAL-PORT RAM
Lifecycle:
New from this manufacturer.
Delivery:
DHL FedEx Ups TNT EMS
Payment:
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